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* Fix some typo/formatting issues. No functionality change.Nick Lewycky2011-10-182-10/+10
| | | | llvm-svn: 142435
* Fix a bug in the legalization of vector anyext-load and trunc-store. Mem ↵Nadav Rotem2011-10-181-7/+9
| | | | | | Index starts with zero. llvm-svn: 142434
* Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson2011-10-181-2/+13
| | | | | | | | | svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. llvm-svn: 142370
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-183-3/+4
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Fix comment to refer to correct instructionHal Finkel2011-10-181-1/+1
| | | | llvm-svn: 142334
* Minor style cleanup, no functionality change.Nick Lewycky2011-10-171-3/+2
| | | | llvm-svn: 142307
* Add support for a new extension to the .file directive:Nick Lewycky2011-10-173-18/+18
| | | | | | | | | | .file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. llvm-svn: 142300
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-171-0/+1
| | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> llvm-svn: 142294
* When deleting a phi cycle after looking through copies, constrain the registerCameron Zwarich2011-10-171-1/+5
| | | | | | | | | to match its final use. With this change, all of test-suite compiles for Thumb2 with -verify-coalescing enabled. llvm-svn: 142287
* Constraint register class with constrainRegClass() to CSE a virtual into ↵Evan Cheng2011-10-171-3/+26
| | | | | | another. rdar://10293289 llvm-svn: 142234
* Correct over-zealous removal of hack.Bill Wendling2011-10-171-1/+1
| | | | | | | Some code want to check that *any* call within a function has the 'returns twice' attribute, not just that the current function has one. llvm-svn: 142221
* Now that we have the ReturnsTwice function attribute, this method isBill Wendling2011-10-171-1/+1
| | | | | | | obsolete. Check the attribute instead. <rdar://problem/8031714> llvm-svn: 142212
* Removed set, but unused variable.Chad Rosier2011-10-171-1/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142206
* It is safe to speculate load from GOT. This fixes performance regression ↵Devang Patel2011-10-171-1/+17
| | | | | | | | caused by r141689. Radar 10281206. llvm-svn: 142202
* Enable element promotion type legalization by deafault.Nadav Rotem2011-10-161-1/+1
| | | | | | Changed tests which assumed that vectors are legalized by widening them. llvm-svn: 142152
* Let printf do the formatting instead aligning strings ourselves.Benjamin Kramer2011-10-161-1/+1
| | | | | | While at it, merge some format strings. llvm-svn: 142140
* Twinify better.Benjamin Kramer2011-10-161-20/+15
| | | | llvm-svn: 142139
* Move the legalization of vector loads and stores into LegalizeVectorOps. In someNadav Rotem2011-10-152-183/+123
| | | | | | cases we need the second type-legalization pass in order to support all cases. llvm-svn: 142060
* Clear out the landing pad to call site map for each function.Bill Wendling2011-10-151-0/+1
| | | | | | | This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. llvm-svn: 142032
* A few 80-col violations.Evan Cheng2011-10-141-1/+2
| | | | llvm-svn: 141988
* Update live-in lists when splitting critical edges.Jakob Stoklund Olesen2011-10-141-0/+5
| | | | | | Fixes PR10814. Patch by Jan Sjödin! llvm-svn: 141960
* Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".Jim Grosbach2011-10-141-1/+1
| | | | | | Pointed out by George Russell. llvm-svn: 141956
* Add value numbers when spilling dead defs.Jakob Stoklund Olesen2011-10-141-1/+9
| | | | | | | | | | | | | | | | When spilling around an instruction with a dead def, remember to add a value number for the def. The missing value number wouldn't normally create problems since there would be an incoming live range as well. However, due to another bug we could spill a dead V_SET0 instruction which doesn't read any values. The missing value number caused an empty live range to be created which is dangerous since it doesn't interfere with anything. This fixes part of PR11125. llvm-svn: 141923
* Don't forget to reconstruct D after changing the scope that we'reEric Christopher2011-10-131-1/+3
| | | | | | looking at. llvm-svn: 141892
* Use an existing method.Cameron Zwarich2011-10-131-1/+1
| | | | llvm-svn: 141855
* If MI is deleted then remove it from the set. If a new MI is created, it couldNick Lewycky2011-10-131-0/+2
| | | | | | | have the same address as the one we deleted, and we don't want that in the set yet. Noticed by inspection. llvm-svn: 141849
* Tabs to spaces.Nick Lewycky2011-10-131-2/+2
| | | | llvm-svn: 141844
* Add missing braces to pacify GCC's -Wparentheses.Nick Lewycky2011-10-131-1/+2
| | | | llvm-svn: 141842
* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-121-4/+1
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. llvm-svn: 141836
* Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen2011-10-121-0/+33
| | | | | | | | | Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. llvm-svn: 141835
* Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen2011-10-121-30/+38
| | | | llvm-svn: 141834
* Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen2011-10-122-8/+29
| | | | | | | | | | | | | The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. llvm-svn: 141833
* We need to verify that the machine instruction we're using as a replacement forBill Wendling2011-10-121-0/+11
| | | | | | | | | | our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830
* Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman2011-10-121-1/+1
| | | | | | behavior. Based on patch by Ahmed Charles. llvm-svn: 141829
* Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng2011-10-121-6/+15
| | | | | | to investigate the regressions. llvm-svn: 141813
* To find the exiting VN of a LiveInterval from a block, use the previous slotCameron Zwarich2011-10-121-1/+1
| | | | | | | | | | | rather than the previous index. If a block has a single instruction, the previous index may be in a different basic block. I have no clue how this used to work on all of test-suite, because now this failure is seen quite often when trying to compile code with -strong-phi-elim. This fixes PR10252. llvm-svn: 141812
* Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman2011-10-121-1/+1
| | | | | | intended, but only by accident. llvm-svn: 141779
* Expand the check for a landing pad so that it looks at the basic block'sBill Wendling2011-10-121-5/+11
| | | | | | | containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. llvm-svn: 141767
* Use an existing function.Jakob Stoklund Olesen2011-10-121-10/+2
| | | | llvm-svn: 141763
* Fix r141744.Evan Cheng2011-10-121-1/+19
| | | | | | | | | 1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. llvm-svn: 141747
* Refine r141689 with a tri-state variable.Evan Cheng2011-10-111-19/+23
| | | | | | Also teach MachineLICM to avoid "speculation" when register pressure is high. llvm-svn: 141744
* Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher2011-10-112-3/+21
| | | | | | | | | | | | | file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 llvm-svn: 141729
* Formatting.Eric Christopher2011-10-111-2/+1
| | | | llvm-svn: 141728
* N.B. This is with the new EH scheme:Bill Wendling2011-10-111-0/+5
| | | | | | | | | | | | | | | The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. llvm-svn: 141726
* Add dominance check for the instruction being hoisted.Devang Patel2011-10-111-1/+46
| | | | | | | For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141689
* Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem2011-10-111-0/+25
| | | | llvm-svn: 141667
* Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem2011-10-111-13/+13
| | | | | | type is illegal (for example, v2i16 on systems where the smallest store size is i32) llvm-svn: 141661
* Cleanup the trunc-store legalization code and add asserts.Nadav Rotem2011-10-111-68/+87
| | | | llvm-svn: 141659
* Revert r141569 and r141576.Devang Patel2011-10-101-29/+0
| | | | llvm-svn: 141594
* Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen2011-10-101-4/+12
| | | | | | | | | | | Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. llvm-svn: 141578
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