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author | Nick Lewycky <nicholas@mxc.ca> | 2011-10-13 00:54:59 +0000 |
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committer | Nick Lewycky <nicholas@mxc.ca> | 2011-10-13 00:54:59 +0000 |
commit | 84882259847e72335b2e5700848b9d200a768cec (patch) | |
tree | 762382c602912c6be4e1dcf7ee4471d3c64e670e /llvm/lib/CodeGen | |
parent | f9799f8181a910e6a130914cf65e3df65ff4aa2b (diff) | |
download | bcm5719-llvm-84882259847e72335b2e5700848b9d200a768cec.tar.gz bcm5719-llvm-84882259847e72335b2e5700848b9d200a768cec.zip |
Add missing braces to pacify GCC's -Wparentheses.
llvm-svn: 141842
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 0ef1ef603b7..a240667f7d6 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1473,11 +1473,12 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { } unsigned RCID = 0; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) + if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { if (TM) OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); else OS << ":RC" << RCID; + } unsigned TiedTo = 0; if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) |