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path: root/llvm/lib/CodeGen/TargetRegisterInfo.cpp
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* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-1/+1
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-2/+5
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-06-191-5/+15
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* BitVector: add iterators for set bitsFrancis Visoiu Mistrih2017-05-171-2/+1
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-3/+3
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-2/+2
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-5/+5
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-241-9/+0
* Correct register pressure calculation in presence of subregsStanislav Mekhanoshin2017-02-231-0/+9
* Cleanup dump() functions.Matthias Braun2017-01-281-3/+3
* Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek2017-01-251-6/+4
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-8/+2
* Clarify rules for reserved regs, fix aarch64 ones.Matthias Braun2016-11-301-0/+30
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-2/+2
* [TargetRegisterInfo] Re-apply r265734.Quentin Colombet2016-04-081-12/+5
* Revert "[TargetRegisterInfo] Refactor the code to use BitMaskClassIterator."Quentin Colombet2016-04-081-5/+12
* [TargetRegisterInfo] Refactor the code to use BitMaskClassIterator.Quentin Colombet2016-04-071-12/+5
* ARM, AArch64, X86: Check preserved registers for tail calls.Matthias Braun2016-04-041-0/+9
* raw_ostream: << operator for callables with raw_ostream argumentMatthias Braun2015-12-041-41/+54
* Revert "raw_ostream: << operator for callables with raw_stream argument"Matthias Braun2015-12-031-54/+41
* raw_ostream: << operator for callables with raw_stream argumentMatthias Braun2015-12-031-41/+54
* [X86] Part 1 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-031-5/+13
* TargetRegisterInfo: Introduce PrintLaneMask.Matthias Braun2015-09-251-0/+5
* Introduce target hook for optimizing register copiesMatt Arsenault2015-09-241-0/+41
* Use function attribute "stackrealign" to decide whether stackAkira Hatanaka2015-09-111-9/+1
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-1/+34
* TargetRegisterInfo: Provide a way to check assigned registers in getRegAlloca...Matthias Braun2015-07-151-1/+2
* Introduce register dump helperMatthias Braun2014-11-191-0/+9
* Convert some EVTs to MVTs where only a SimpleValueType is needed.Craig Topper2014-11-161-1/+1
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper2014-04-141-6/+6
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
* PrintVRegOrUnitAndrew Trick2013-08-231-0/+8
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-2/+2
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-161-2/+4
* Remove unneeded "TargetMachine.h" #includes.Jakub Staszak2013-02-091-1/+0
* Add a new hook for providing register allocator hints more flexibly.Jakob Stoklund Olesen2012-12-031-0/+38
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-1/+1
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-281-0/+248
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