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authorJakob Stoklund Olesen <stoklund@2pi.dk>2013-05-16 18:03:08 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2013-05-16 18:03:08 +0000
commit9ae96c7aab27b88d44221c7de30305fcafb78024 (patch)
treebdb436593ac9c7785054551732e5507281fec53e /llvm/lib/CodeGen/TargetRegisterInfo.cpp
parentd819aa5c54a5036c995c7024d709d42998db601b (diff)
downloadbcm5719-llvm-9ae96c7aab27b88d44221c7de30305fcafb78024.tar.gz
bcm5719-llvm-9ae96c7aab27b88d44221c7de30305fcafb78024.zip
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
Diffstat (limited to 'llvm/lib/CodeGen/TargetRegisterInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetRegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 84b4bfc3322..4c21daf07a5 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -23,10 +23,12 @@ using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *SRINames,
- const unsigned *SRILaneMasks)
+ const unsigned *SRILaneMasks,
+ unsigned SRICoveringLanes)
: InfoDesc(ID), SubRegIndexNames(SRINames),
SubRegIndexLaneMasks(SRILaneMasks),
- RegClassBegin(RCB), RegClassEnd(RCE) {
+ RegClassBegin(RCB), RegClassEnd(RCE),
+ CoveringLanes(SRICoveringLanes) {
}
TargetRegisterInfo::~TargetRegisterInfo() {}
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