diff options
| author | Francis Visoiu Mistrih <fvisoiumistrih@apple.com> | 2017-05-17 01:07:53 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <fvisoiumistrih@apple.com> | 2017-05-17 01:07:53 +0000 |
| commit | b52e0366008436f6f994ce94cb6ad0f51d65ba8a (patch) | |
| tree | c6067844f69347f2f77a9094caff2644ddcffcf6 /llvm/lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | de83fec0299ac4bae25d7e36ef30feddba2b48ad (diff) | |
| download | bcm5719-llvm-b52e0366008436f6f994ce94cb6ad0f51d65ba8a.tar.gz bcm5719-llvm-b52e0366008436f6f994ce94cb6ad0f51d65ba8a.zip | |
BitVector: add iterators for set bits
Differential revision: https://reviews.llvm.org/D32060
llvm-svn: 303227
Diffstat (limited to 'llvm/lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetRegisterInfo.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index f6e4c17d514..41ec082a24c 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -50,8 +50,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef<MCPhysReg> Exceptions) const { // Check that all super registers of reserved regs are reserved as well. BitVector Checked(getNumRegs()); - for (int Reg = RegisterSet.find_first(); Reg>=0; - Reg = RegisterSet.find_next(Reg)) { + for (unsigned Reg : RegisterSet.set_bits()) { if (Checked[Reg]) continue; for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { |
