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path: root/llvm/lib/CodeGen/TargetRegisterInfo.cpp
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* [TargetRegisterInfo] Remove SVT argument from getCommonSubClass.Craig Topper2019-09-131-13/+5
* Eliminate implicit Register->unsigned conversions in VirtRegMap. NFCDaniel Sanders2019-08-131-1/+1
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-14/+15
* Reland "[DwarfDebug] Dump call site debug info"Djordje Todorovic2019-07-311-0/+13
* Revert "[DwarfDebug] Dump call site debug info"Djordje Todorovic2019-07-121-14/+0
* [DwarfDebug] Dump call site debug infoDjordje Todorovic2019-07-091-0/+14
* [RegAlloc] Avoid compile time regression with multiple copy hints.Jonas Paulsson2019-03-111-0/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-1/+2
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-4/+10
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-231-0/+23
* Revert [MachineLICM] This reverts commit rL327856Zaara Syeda2018-03-191-23/+0
* [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-191-0/+23
* [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar2018-02-021-0/+22
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-3/+3
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-5/+5
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-0/+15
* [Regalloc] Generate and store multiple regalloc hints.Jonas Paulsson2017-12-051-25/+30
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-2/+5
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-2/+2
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-3/+5
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-7/+7
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
* [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.Jonas Paulsson2017-11-101-4/+5
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-1/+1
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-2/+5
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-06-191-5/+15
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* BitVector: add iterators for set bitsFrancis Visoiu Mistrih2017-05-171-2/+1
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-3/+3
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-2/+2
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-5/+5
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-241-9/+0
* Correct register pressure calculation in presence of subregsStanislav Mekhanoshin2017-02-231-0/+9
* Cleanup dump() functions.Matthias Braun2017-01-281-3/+3
* Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek2017-01-251-6/+4
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-8/+2
* Clarify rules for reserved regs, fix aarch64 ones.Matthias Braun2016-11-301-0/+30
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-2/+2
* [TargetRegisterInfo] Re-apply r265734.Quentin Colombet2016-04-081-12/+5
* Revert "[TargetRegisterInfo] Refactor the code to use BitMaskClassIterator."Quentin Colombet2016-04-081-5/+12
* [TargetRegisterInfo] Refactor the code to use BitMaskClassIterator.Quentin Colombet2016-04-071-12/+5
* ARM, AArch64, X86: Check preserved registers for tail calls.Matthias Braun2016-04-041-0/+9
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