summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Add 'const' qualifier to some arrays.Craig Topper2013-07-151-1/+2
| | | | llvm-svn: 186312
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-11/+11
| | | | | | size. llvm-svn: 186274
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-251-1/+1
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig2013-03-201-18/+12
| | | | | | | | | | | This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 177529
* pre-RA-sched: fix TargetOpcode usageChristian Konig2013-03-201-12/+18
| | | | | | | TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 177518
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
| | | | llvm-svn: 176638
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
| | | | | | | | | | | | | rdar:13370002 [pre-RA-sched] assertion: released too many times I tracked this down to an earlier hack that is no longer applicable and interfered with normal scheduler logic. With the changes in r176037, it was causing an instruction to be scheduled multiple times. I have an external test case that I tried hard to reduce and failed. I can't even reproduce with llc. llvm-svn: 176636
* pre-RA-sched fix: only reevaluate physreg interferences when necessary.Andrew Trick2013-02-251-33/+61
| | | | | | Fixes rdar:13279013: scheduler was blowing up on select instructions. llvm-svn: 176037
* Add a special handling case for untyped CopyFromReg node in GetCostForDef() ↵Weiming Zhao2013-01-291-1/+11
| | | | | | of ScheduleDAGRRList llvm-svn: 173833
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-8/+8
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-8/+8
| | | | llvm-svn: 169854
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-8/+8
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-10/+10
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-1/+1
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-22/+14
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. llvm-svn: 167435
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* Release build: guard dump functions withManman Ren2012-09-111-2/+2
| | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. llvm-svn: 163653
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+4
| | | | | | No functional change. llvm-svn: 163339
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+2
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | llvm-svn: 160621
* sdsched: Use the right heuristics when -mcpu is not provided and we have no ↵Andrew Trick2012-06-051-13/+12
| | | | | | | | itinerary. Use ILP heuristics for long latency instrs if no scoreboard exists. llvm-svn: 157978
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-1/+1
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Mark some static arrays as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157377
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-5/+6
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng2012-03-221-7/+11
| | | | | | rdar://11096639 llvm-svn: 153270
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-6/+6
| | | | llvm-svn: 152301
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-12/+12
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+6
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-1/+1
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | llvm-svn: 152001
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
* Make sure we correctly set LiveRegGens when a call is unscheduled. ↵Eli Friedman2011-12-071-1/+8
| | | | | | <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling. llvm-svn: 146087
* Fix an assertion in the scheduler. PR11386. No testcase included because ↵Eli Friedman2011-12-071-3/+2
| | | | | | it's rather delicate. llvm-svn: 146083
* These global variables aren't thread-safe, STATISTIC is. Andy Trick tells meNick Lewycky2011-12-071-66/+12
| | | | | | that he isn't using these any more, so just delete them. llvm-svn: 146076
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-2/+2
| | | | llvm-svn: 144747
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS ↵Pete Cooper2011-11-151-0/+5
| | | | | | | | | | | | registers is used by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> llvm-svn: 144705
* Use a bigger hammer to fix PR11314 by disabling the "forcing two-addressEvan Cheng2011-11-101-1/+5
| | | | | | | | | | | | | | | | instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. llvm-svn: 144267
* Speculatively revert commit 144124 (djg) in the hope that the 32 bitDuncan Sands2011-11-091-13/+3
| | | | | | | | | | | | | | dragonegg self-host buildbot will recover (it is complaining about object files differing between different build stages). Original commit message: Add a hack to the scheduler to disable pseudo-two-address dependencies in basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. llvm-svn: 144188
* Add a hack to the scheduler to disable pseudo-two-address dependencies inDan Gohman2011-11-081-3/+13
| | | | | | | | | | basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. llvm-svn: 144124
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-031-2/+181
| | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. llvm-svn: 143660
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-291-163/+2
| | | | llvm-svn: 143262
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-281-2/+163
| | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-134/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-4/+4
| | | | | | use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
* Remove a now dead function, fixing -Wunused-function warnings fromChandler Carruth2011-10-211-20/+0
| | | | | | Clang. llvm-svn: 142631
* Delete the list-tdrr scheduler. Top-down schedulers are going awayDan Gohman2011-10-201-203/+11
| | | | | | because they don't support physical register dependencies. llvm-svn: 142620
* PreRA scheduler should avoid cloning compares.Andrew Trick2011-09-011-1/+35
| | | | | | | | | Added canClobberReachingPhysRegUse() to handle a particular pattern in which a two-address instruction could be forced to interfere with EFLAGS, causing a compare to be unnecessarilly cloned. Fixes rdar://problem/5875261 llvm-svn: 138924
OpenPOWER on IntegriCloud