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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 16:12:24 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 16:12:24 +0000 |
| commit | c71cced0aae46ab4f27e2ea755819f308661670b (patch) | |
| tree | e63f1794dd2fed8bf926665dc8aa53abc7e13048 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | 0cdf7fdc48fd024a55df2afd773d0f7359a79736 (diff) | |
| download | bcm5719-llvm-c71cced0aae46ab4f27e2ea755819f308661670b.tar.gz bcm5719-llvm-c71cced0aae46ab4f27e2ea755819f308661670b.zip | |
[CodeGen] Always use `printReg` to print registers in both MIR and debug
output
As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.
Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.
Differential Revision: https://reviews.llvm.org/D40421
llvm-svn: 319445
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index acbae1bae33..a83f4eff383 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1430,10 +1430,12 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { SmallVector<unsigned, 4> LRegs; if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) break; - DEBUG(dbgs() << " Interfering reg " << - (LRegs[0] == TRI->getNumRegs() ? "CallResource" - : TRI->getName(LRegs[0])) - << " SU #" << CurSU->NodeNum << '\n'); + DEBUG(dbgs() << " Interfering reg "; + if (LRegs[0] == TRI->getNumRegs()) + dbgs() << "CallResource"; + else + dbgs() << printReg(LRegs[0], TRI); + dbgs() << " SU #" << CurSU->NodeNum << '\n'); std::pair<LRegsMapT::iterator, bool> LRegsPair = LRegsMap.insert(std::make_pair(CurSU, LRegs)); if (LRegsPair.second) { |
