bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	misched prep: Expose the ScheduleDAGInstrs interface so targets may	Andrew Trick	2012-03-07	1	-339/+0
*	misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.	Andrew Trick	2012-03-07	1	-2/+2
*	misched prep: Comment the ScheduleDAGInstrs interface.	Andrew Trick	2012-03-07	1	-7/+12
*	misched prep: Cleanup ScheduleDAGInstrs interface.	Andrew Trick	2012-03-07	1	-73/+79
*	misched prep: remove extra "protected"	Andrew Trick	2012-03-07	1	-2/+0
*	misched prep: rename InsertPos to End.	Andrew Trick	2012-03-07	1	-8/+6
*	misched preparation: rename core scheduler methods for consistency.	Andrew Trick	2012-03-07	1	-16/+16
*	comment	Andrew Trick	2012-03-07	1	-0/+2
*	misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.	Andrew Trick	2012-03-07	1	-18/+38
*	ScheduleDAGInstrs comments	Andrew Trick	2012-03-07	1	-0/+2
*	misched preparation: modularize schedule emission.	Andrew Trick	2012-03-07	1	-2/+0
*	Cleanup in preparation for misched: Move DAG visualization logic.	Andrew Trick	2012-03-07	1	-0/+2
*	Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...	Andrew Trick	2012-03-07	1	-1/+1
*	misched comments	Andrew Trick	2012-03-07	1	-0/+2
*	ScheduleDAGInstrs.h:155: warning: suggest parentheses around `&&' within `\|\|'.	Nick Lewycky	2012-02-24	1	-1/+1
*	PostRA sched: speed up physreg tracking by not abusing SparseSet.	Andrew Trick	2012-02-24	1	-20/+54
*	PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.	Andrew Trick	2012-02-23	1	-6/+18
*	misched: Use SparseSet for VRegDegs for constant time clear().	Andrew Trick	2012-02-22	1	-3/+22
*	Initialize SUnits before DAG building.	Andrew Trick	2012-02-22	1	-7/+20
*	misched: Initial code for building an MI level scheduling DAG	Andrew Trick	2012-01-14	1	-2/+12
*	Move physreg dependency generation into aptly named addPhysRegDeps.	Andrew Trick	2012-01-14	1	-0/+7
*	misched: Added ScheduleDAGInstrs::IsPostRA	Andrew Trick	2012-01-14	1	-5/+9
*	Added a late machine instruction copy propagation pass. This catches	Evan Cheng	2012-01-07	1	-5/+0
*	PostRA scheduler fix. Clear stale loop dependencies.	Andrew Trick	2011-10-07	1	-1/+2
*	whitespace	Andrew Trick	2011-10-07	1	-2/+2
*	Update DBG_VALUEs while breaking anti dependencies.	Devang Patel	2011-06-02	1	-4/+8
*	During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...	Devang Patel	2011-06-02	1	-3/+3
*	Properly model the latency of register defs which are 1) function returns or	Evan Cheng	2010-10-23	1	-0/+9
*	Teach if-converter to be more careful with predicating instructions that would	Evan Cheng	2010-09-10	1	-0/+1
*	Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors	Bob Wilson	2010-07-24	1	-2/+2
*	When processing loops for scheduling latencies (used for live outs on loop	Jim Grosbach	2010-06-29	1	-1/+4
*	I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it	Duncan Sands	2010-05-11	1	-2/+2
*	Get rid of the EdgeMapping map. Instead, just check for BasicBlock	Dan Gohman	2010-05-01	1	-3/+1
*	Progress towards shepherding debug info through SelectionDAG.	Dale Johannesen	2010-03-10	1	-0/+4
*	Spill slots cannot alias.	Evan Cheng	2009-10-18	1	-0/+1
*	Remove a redundant member variable.	Dan Gohman	2009-10-12	1	-1/+0
*	Factor out LiveIntervalAnalysis' code to determine whether an instruction	Dan Gohman	2009-10-09	1	-1/+1
*	Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ...	Evan Cheng	2009-09-18	1	-2/+4
*	Use the schedule itinerary operand use/def cycle information to adjust depend...	David Goodwin	2009-08-19	1	-0/+6
*	When scheduling a block in parts, keep track of the overall	Dan Gohman	2009-02-11	1	-0/+13
*	Factor out more code for computing register live-range informationfor	Dan Gohman	2009-02-10	1	-1/+90
*	Move ScheduleDAGInstrs.h to be a private header. Front-ends	Dan Gohman	2009-02-06	1	-0/+82