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| author | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:15 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:15 +0000 |
| commit | dbee9d8900a33423b3d50b357c05db5d0776194a (patch) | |
| tree | d94a1aaf85aecab84fdcbd7135cb2ab079118d20 /llvm/lib/CodeGen/ScheduleDAGInstrs.h | |
| parent | 1d028a364d6fcee53f163ad2d3fa754a7fb860f5 (diff) | |
| download | bcm5719-llvm-dbee9d8900a33423b3d50b357c05db5d0776194a.tar.gz bcm5719-llvm-dbee9d8900a33423b3d50b357c05db5d0776194a.zip | |
Move physreg dependency generation into aptly named addPhysRegDeps.
llvm-svn: 148173
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.h')
| -rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/llvm/lib/CodeGen/ScheduleDAGInstrs.h index f3932892563..55da5c08181 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.h +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.h @@ -107,6 +107,9 @@ namespace llvm { /// isPostRA flag indicates vregs cannot be present. bool IsPostRA; + /// UnitLatencies flag forces single-cycle data dependencies. + bool UnitLatencies; + /// Defs, Uses - Remember where defs and uses of each register are as we /// iterate upward through the instructions. This is allocated here instead /// of inside BuildSchedGraph to avoid the need for it to be initialized and @@ -205,6 +208,10 @@ namespace llvm { virtual void dumpNode(const SUnit *SU) const; virtual std::string getGraphNodeLabel(const SUnit *SU) const; + + protected: + void addPhysRegDeps(SUnit *SU, unsigned OperIdx); + void addVirtRegDeps(SUnit *SU, unsigned OperIdx); }; } |

