diff options
author | Dan Gohman <gohman@apple.com> | 2009-02-06 17:12:10 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2009-02-06 17:12:10 +0000 |
commit | f4b08b4f6c7037e90b348303395fd877cd819b83 (patch) | |
tree | a61706fe972f17dd63b7097c4d17edcdb0ca865c /llvm/lib/CodeGen/ScheduleDAGInstrs.h | |
parent | 1731125787f8e782d789bbd1c4d883d31c676e3f (diff) | |
download | bcm5719-llvm-f4b08b4f6c7037e90b348303395fd877cd819b83.tar.gz bcm5719-llvm-f4b08b4f6c7037e90b348303395fd877cd819b83.zip |
Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).
llvm-svn: 63934
Diffstat (limited to 'llvm/lib/CodeGen/ScheduleDAGInstrs.h')
-rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/llvm/lib/CodeGen/ScheduleDAGInstrs.h new file mode 100644 index 00000000000..3a10b5e4de9 --- /dev/null +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.h @@ -0,0 +1,82 @@ +//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the ScheduleDAGInstrs class, which implements +// scheduling for a MachineInstr-based dependency graph. +// +//===----------------------------------------------------------------------===// + +#ifndef SCHEDULEDAGINSTRS_H +#define SCHEDULEDAGINSTRS_H + +#include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Target/TargetRegisterInfo.h" + +namespace llvm { + class MachineLoopInfo; + class MachineDominatorTree; + + class ScheduleDAGInstrs : public ScheduleDAG { + const MachineLoopInfo &MLI; + const MachineDominatorTree &MDT; + + /// Defs, Uses - Remember where defs and uses of each physical register + /// are as we iterate upward through the instructions. This is allocated + /// here instead of inside BuildSchedGraph to avoid the need for it to be + /// initialized and destructed for each block. + std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister]; + std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister]; + + /// PendingLoads - Remember where unknown loads are after the most recent + /// unknown store, as we iterate. As with Defs and Uses, this is here + /// to minimize construction/destruction. + std::vector<SUnit *> PendingLoads; + + public: + explicit ScheduleDAGInstrs(MachineFunction &mf, + const MachineLoopInfo &mli, + const MachineDominatorTree &mdt); + + virtual ~ScheduleDAGInstrs() {} + + /// NewSUnit - Creates a new SUnit and return a ptr to it. + /// + SUnit *NewSUnit(MachineInstr *MI) { +#ifndef NDEBUG + const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0]; +#endif + SUnits.push_back(SUnit(MI, (unsigned)SUnits.size())); + assert((Addr == 0 || Addr == &SUnits[0]) && + "SUnits std::vector reallocated on the fly!"); + SUnits.back().OrigNode = &SUnits.back(); + return &SUnits.back(); + } + + /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are + /// input. + virtual void BuildSchedGraph(); + + /// ComputeLatency - Compute node latency. + /// + virtual void ComputeLatency(SUnit *SU); + + virtual MachineBasicBlock *EmitSchedule(); + + /// Schedule - Order nodes according to selected style, filling + /// in the Sequence member. + /// + virtual void Schedule() = 0; + + virtual void dumpNode(const SUnit *SU) const; + + virtual std::string getGraphNodeLabel(const SUnit *SU) const; + }; +} + +#endif |