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-rw-r--r--llvm/test/MC/ARM/neon-vcvt-fp16.s18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/neon-vcvt-fp16.s b/llvm/test/MC/ARM/neon-vcvt-fp16.s
new file mode 100644
index 00000000000..a23be061c0f
--- /dev/null
+++ b/llvm/test/MC/ARM/neon-vcvt-fp16.s
@@ -0,0 +1,18 @@
+@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \
+@ RUN: FileCheck %s --check-prefix=CHECK-FP16
+@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \
+@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16
+
+@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
+@ CHECK-NOFP16: instruction requires: half-float conversions
+ vcvtt.f32.f16 s7, s1
+@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
+@ CHECK-NOFP16: instruction requires: half-float conversions
+ vcvtt.f16.f32 s1, s7
+
+@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
+@ CHECK-NOFP16: instruction requires: half-float conversions
+ vcvtb.f32.f16 s7, s1
+@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
+@ CHECK-NOFP16: instruction requires: half-float conversions
+ vcvtb.f16.f32 s1, s7
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