diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/build-attributes.ll | 2 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/neon-vcvt-fp16.s | 18 |
4 files changed, 28 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index dd33c3614b1..a44dc830a67 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -585,6 +585,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, FeatureVFP3, FeatureVFPOnlySP, FeatureD16, + FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 2aea73a6336..050cd1a445a 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -540,19 +540,23 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, // FIXME: Verify encoding after integrated assembler is working. def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", - [/* For disassembly only; pattern left blank */]>; + [/* For disassembly only; pattern left blank */]>, + Requires<[HasFP16]>; def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", - [/* For disassembly only; pattern left blank */]>; + [/* For disassembly only; pattern left blank */]>, + Requires<[HasFP16]>; def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", - [/* For disassembly only; pattern left blank */]>; + [/* For disassembly only; pattern left blank */]>, + Requires<[HasFP16]>; def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", - [/* For disassembly only; pattern left blank */]>; + [/* For disassembly only; pattern left blank */]>, + Requires<[HasFP16]>; def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs DPR:$Dd), (ins SPR:$Sm), diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index b80191d7601..bf502b3ae07 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -1105,7 +1105,7 @@ ; CORTEX-R7: .eabi_attribute 25, 1 ; CORTEX-R7: .eabi_attribute 27, 1 ; CORTEX-R7-NOT: .eabi_attribute 28 -; CORTEX-R7-NOT: .eabi_attribute 36 +; CORTEX-R7: .eabi_attribute 36, 1 ; CORTEX-R7: .eabi_attribute 38, 1 ; CORTEX-R7: .eabi_attribute 42, 1 ; CORTEX-R7: .eabi_attribute 44, 2 diff --git a/llvm/test/MC/ARM/neon-vcvt-fp16.s b/llvm/test/MC/ARM/neon-vcvt-fp16.s new file mode 100644 index 00000000000..a23be061c0f --- /dev/null +++ b/llvm/test/MC/ARM/neon-vcvt-fp16.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \ +@ RUN: FileCheck %s --check-prefix=CHECK-FP16 +@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \ +@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16 + +@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f32.f16 s7, s1 +@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f16.f32 s1, s7 + +@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f32.f16 s7, s1 +@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f16.f32 s1, s7 |
