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| author | Bradley Smith <bradley.smith@arm.com> | 2015-12-07 10:54:36 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2015-12-07 10:54:36 +0000 |
| commit | d5a1f47a63f95cc44f4fde3020d04ee09f70a16c (patch) | |
| tree | a42a765e86d254f3e37d81c675ac5fd043346e20 /llvm/test/MC/ARM | |
| parent | b825de17b73f92c05ab174f02a221865702716f9 (diff) | |
| download | bcm5719-llvm-d5a1f47a63f95cc44f4fde3020d04ee09f70a16c.tar.gz bcm5719-llvm-d5a1f47a63f95cc44f4fde3020d04ee09f70a16c.zip | |
[ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extension
Additionally correct the Cortex-R7 definition to allow the FP16 feature.
llvm-svn: 254900
Diffstat (limited to 'llvm/test/MC/ARM')
| -rw-r--r-- | llvm/test/MC/ARM/neon-vcvt-fp16.s | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/neon-vcvt-fp16.s b/llvm/test/MC/ARM/neon-vcvt-fp16.s new file mode 100644 index 00000000000..a23be061c0f --- /dev/null +++ b/llvm/test/MC/ARM/neon-vcvt-fp16.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \ +@ RUN: FileCheck %s --check-prefix=CHECK-FP16 +@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \ +@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16 + +@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f32.f16 s7, s1 +@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f16.f32 s1, s7 + +@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f32.f16 s7, s1 +@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f16.f32 s1, s7 |
