Renamed generate to forgen and for to forloop

4 files changed, 19 insertions, 16 deletions

diff --git a/examples/generate.vhd b/examples/forgen.vhd
index 30246c1..61f11fe 100644
--- a/examples/generate.vhd
+++ b/examples/forgen.vhd
@@ -1,16 +1,19 @@
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
-entity gen is   generic(
-  bus_width : integer := 15;
-  TOP_GP2 : integer:= 0
+
+entity forgen is
+  generic(
+    bus_width : integer := 15;
+    TOP_GP2 : integer:= 0
+  );
+  port(
+    sysclk, reset, wrb : in std_logic;
+    din : in std_logic_vector(bus_width downto 0);
+    rdout: out std_logic_vector(bus_width downto 0)
   );
-                port(
-                  sysclk, reset, wrb : in std_logic;
-                  din : in std_logic_vector(bus_width downto 0);
-                  rdout: out std_logic_vector(bus_width downto 0)
-);
-end gen;
-architecture rtl of gen is
+end forgen;
+
+architecture rtl of forgen is
   component wbit1                       -- register bit default 1
     port(
       clk   : in  std_logic;
diff --git a/examples/for.vhd b/examples/forloop.vhd
index 71ff3a5..241b8c7 100644
--- a/examples/for.vhd
+++ b/examples/forloop.vhd
@@ -1,12 +1,13 @@
 library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
-entity forp is port(
+
+entity forloop is port(
   reset, sysclk : in std_logic
 );
-end forp;
-architecture rtl of forp is
+end forloop;
 
+architecture rtl of forloop is
   signal selection : std_logic;
   signal egg_timer : std_logic_vector(6 downto 0);
 begin
@@ -33,5 +34,4 @@ begin
       end loop;  -- i
     end if;
   end process;
-
 end rtl;
diff --git a/translated_examples/generate.v b/translated_examples/forgen.v
index b96a6b3..96be6cf 100644
--- a/translated_examples/generate.v
+++ b/translated_examples/forgen.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module gen(
+module forgen(
 input wire sysclk,
 input wire reset,
 input wire wrb,
diff --git a/translated_examples/for.v b/translated_examples/forloop.v
index ce31bc7..88ee5f7 100644
--- a/translated_examples/for.v
+++ b/translated_examples/forloop.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module forp(
+module forloop(
 input wire reset,
 input wire sysclk
 );