Moved unsupported commented things to todo.vhd

8 files changed, 64 insertions, 9 deletions

diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
index a9624ba..5897f16 100644
--- a/examples/bigfile.vhd
+++ b/examples/bigfile.vhd
@@ -227,8 +227,6 @@ begin
             if( n9_bit_write = '1' ) then
               -- set
               g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
-            else
-              -- XXX not ready for exit;
             end if;
           --vnavigatoroff
           else
diff --git a/examples/forloop.vhd b/examples/forloop.vhd
index 241b8c7..492ec27 100644
--- a/examples/forloop.vhd
+++ b/examples/forloop.vhd
@@ -13,7 +13,7 @@ architecture rtl of forloop is
 begin
   TIMERS :
   process(reset, sysclk)
-    variable timer_var : integer; -- XXX unhandled := 0;
+    variable timer_var : integer;
     variable a, i, j, k : integer;
     variable zz5 : std_logic_vector(31 downto 0);
     variable zz : std_logic_vector(511 downto 0);
diff --git a/examples/partselect.vhd b/examples/partselect.vhd
index 86dc073..90c67b2 100644
--- a/examples/partselect.vhd
+++ b/examples/partselect.vhd
@@ -16,7 +16,7 @@ begin
    test_i: process(clk_i)
       variable big_var : std_logic_vector(31 downto 0);
       variable lit_var : std_logic_vector(0 to 31);
-      variable j       : integer; -- XXX not ready for :=8;
+      variable j       : integer;
    begin
       if rising_edge(clk_i) then
          big_sig(31 downto 24) <= big_sig(7 downto 0);
diff --git a/examples/todo.vhd b/examples/todo.vhd
index 0144597..c0cdbd9 100644
--- a/examples/todo.vhd
+++ b/examples/todo.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 entity todo is
    port (
+      clk_i  : in  std_logic;
       data_i : in  std_logic_vector(7 downto 0);
       data_o : out std_logic_vector(7 downto 0)
    );
@@ -19,6 +20,17 @@ begin
    --**************************************************************************
    -- Wrong translations
    --**************************************************************************
+   --
+   test_i: process(clk_i)
+      -- iverilog: variable declaration assignments are only allowed at the module level.
+      variable i : integer:=8;
+   begin
+      for i in 0 to 7 loop
+          if i=4 then
+             exit; -- iverilog: error: malformed statement
+          end if;
+      end loop;
+   end process test_i;
 
    --**************************************************************************
    -- Translations which abort with syntax error (uncomment to test)
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index 974dc55..135cf09 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -176,9 +176,6 @@ wire [31:0] g_dout_i;
               // set
               g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b1};
             end
-            else begin
-              // XXX not ready for exit;
-            end
             //vnavigatoroff
           end
           else begin
diff --git a/translated_examples/forloop.v b/translated_examples/forloop.v
index 88ee5f7..c54d382 100644
--- a/translated_examples/forloop.v
+++ b/translated_examples/forloop.v
@@ -13,7 +13,6 @@ reg [6:0] egg_timer;
 
   always @(posedge reset, posedge sysclk) begin : P1
     reg [31:0] timer_var;
-  // XXX unhandled := 0;
     reg [31:0] a, i, j, k;
     reg [31:0] zz5;
     reg [511:0] zz;
diff --git a/translated_examples/partselect.v b/translated_examples/partselect.v
index 11ec901..c6d46a3 100644
--- a/translated_examples/partselect.v
+++ b/translated_examples/partselect.v
@@ -15,7 +15,6 @@ wire [31:0] i = 8;
     reg [31:0] big_var;
     reg [0:31] lit_var;
     reg [31:0] j;
-  // XXX not ready for :=8;
 
     big_sig[31:24] <= big_sig[7:0];
     big_var[31:24] = big_var[7:0];
diff --git a/translated_examples/todo.v b/translated_examples/todo.v
new file mode 100644
index 0000000..6f4fe72
--- /dev/null
+++ b/translated_examples/todo.v
@@ -0,0 +1,50 @@
+// no timescale needed
+
+module todo(
+input wire clk_i,
+input wire [7:0] data_i,
+output wire [7:0] data_o
+);
+
+
+
+
+
+wire [31:0] mem[0:255];
+wire [31:0] int;
+wire [7:0] uns;
+
+  //**************************************************************************
+  // Wrong translations
+  //**************************************************************************
+  //
+  always @(clk_i) begin : P1
+  // iverilog: variable declaration assignments are only allowed at the module level.
+    reg [31:0] i = 8;
+
+    for (i=0; i <= 7; i = i + 1) begin
+      if(i == 4) begin
+        disable;  //VHD2VL: add block name here
+        // iverilog: error: malformed statement
+      end
+    end
+  end
+
+    //**************************************************************************
+  // Translations which abort with syntax error (uncomment to test)
+  //**************************************************************************
+  // Concatenation in port assignament fail
+  //   uns <= "0000" & X"1"; -- It is supported
+  //   dut1_i: signextend
+  //      port map (
+  //        i => "00000000" & X"11", -- But here fail
+  //        o => open
+  //      );
+  // Unsupported type of instantiation
+  //   dut2_i: entity work.signextend
+  //   port map (
+  //      i => (others => '0'),
+  //      o => open
+  //   );
+
+endmodule