Merge pull request #8 from ldoolitt/exclude

Implemented a mechanism to exclude files in the main Makefile

5 files changed, 29 insertions, 22 deletions

diff --git a/Makefile b/Makefile
index 0c29395..1d18df6 100644
--- a/Makefile
+++ b/Makefile
@@ -1,29 +1,38 @@
 #!/usr/bin/make
 
-VHDLS  = $(wildcard examples/*.vhd)
-VHDLS := $(notdir $(VHDLS))
-VHDLS := $(filter-out todo.vhd,$(VHDLS))
+TEMP     = temp
+
+EXCLUDE  = $(shell cat examples/exclude)
+EXCLUDE := $(basename $(EXCLUDE))
+EXCLUDE := $(addsuffix .vhd,$(EXCLUDE))
+
+VHDLS    = $(wildcard examples/*.vhd)
+VHDLS   := $(notdir $(VHDLS))
+
+DIFFOPT  = --exclude=Makefile
+
+ifndef WIP
+VHDLS   := $(filter-out $(EXCLUDE),$(VHDLS))
+DIFFOPT := $(DIFFOPT) --exclude-from=examples/exclude
+endif
 
 all: diff
 
 translate:
 	@make -C src
 	@make -C examples
-	@mkdir -p temp/verilog
+	@rm -fr $(TEMP)/verilog
+	@mkdir $(TEMP)/verilog
 	@echo "##### Translating Examples #####################################"
 	@cd examples; $(foreach VHDL,$(VHDLS), echo "Translating: $(VHDL)";\
-	../src/vhd2vl --quiet $(VHDL) ../temp/verilog/$(basename $(VHDL)).v;)
+	../src/vhd2vl --quiet $(VHDL) ../$(TEMP)/verilog/$(basename $(VHDL)).v;)
 	@make -C translated_examples
 
 diff: translate
 	@echo "##### Diff #####################################################"
-	diff -u --exclude=Makefile translated_examples temp/verilog
+	diff -u $(DIFFOPT) translated_examples $(TEMP)/verilog
 	@echo "PASS"
 
-todo:
-	@make -C src
-	src/vhd2vl --quiet examples/todo.vhd temp/todo.v
-
 clean:
 	make -C src clean
-	rm -fr temp
+	rm -fr $(TEMP)
diff --git a/examples/exclude b/examples/exclude
new file mode 100644
index 0000000..fbffd05
--- /dev/null
+++ b/examples/exclude
@@ -0,0 +1,4 @@
+todo.*
+bigfile.*
+for.*
+partselect.*
diff --git a/examples/ifchain2.vhd b/examples/ifchain2.vhd
index 837dace..b002568 100644
--- a/examples/ifchain2.vhd
+++ b/examples/ifchain2.vhd
@@ -2,14 +2,14 @@ LIBRARY IEEE;
 USE IEEE.std_logic_1164.all;
 USE IEEE.numeric_std.all;
 
-entity ifchain is port(
+entity ifchain2 is port(
   clk, rstn : in std_logic;
   enable: in std_logic;
   result: out std_logic
 );
-end ifchain;
+end ifchain2;
 
-architecture rtl of ifchain is
+architecture rtl of ifchain2 is
   signal counter : unsigned(3 downto 0);
   constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4);
 begin
diff --git a/translated_examples/Makefile b/translated_examples/Makefile
index 6ab476d..88f5081 100644
--- a/translated_examples/Makefile
+++ b/translated_examples/Makefile
@@ -1,14 +1,8 @@
 #!/usr/bin/make
 
-TEMP = ../temp/verilog
-
 all:
 ifneq ($(shell which iverilog),)
-	@mkdir -p $(TEMP)
 	@echo "##### Checking resulting Verilog files with iverilog ###########"
-	@-cd $(TEMP); $(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\
+	@$(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\
 	iverilog -Wall -y . -t null $(VERILOG);)
 endif
-
-clean:
-	rm -fr $(TEMP)
diff --git a/translated_examples/ifchain2.v b/translated_examples/ifchain2.v
index 53e223d..3208dcf 100644
--- a/translated_examples/ifchain2.v
+++ b/translated_examples/ifchain2.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module ifchain(
+module ifchain2(
 input wire clk,
 input wire rstn,
 input wire enable,