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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-11-26 10:03:33 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-11-26 10:03:33 -0300 |
| commit | 4d76e5796e9bcaf5b615ffe6050b2811bad0f97d (patch) | |
| tree | f438ef2c5e97116ec72c7b21b8ead28b22398293 | |
| parent | 4a6ffd6f8ac9b073146632ca0e509b0f54b3fe9c (diff) | |
| download | vhdl2vl-4d76e5796e9bcaf5b615ffe6050b2811bad0f97d.tar.gz vhdl2vl-4d76e5796e9bcaf5b615ffe6050b2811bad0f97d.zip | |
Changed translated_examples/Makefile to analyze individually again
| -rw-r--r-- | translated_examples/Makefile | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/translated_examples/Makefile b/translated_examples/Makefile index b4bfad1..88f5081 100644 --- a/translated_examples/Makefile +++ b/translated_examples/Makefile @@ -1,12 +1,8 @@ #!/usr/bin/make -TEMP = ../temp/verilog - all: ifneq ($(shell which iverilog),) @echo "##### Checking resulting Verilog files with iverilog ###########" - -cd $(TEMP); iverilog -Wall -y . -t null *.v + @$(foreach VERILOG,$(wildcard *.v), echo "Checking: $(VERILOG)";\ + iverilog -Wall -y . -t null $(VERILOG);) endif - -clean: - rm -fr $(TEMP) |
