Merge pull request #7 from ldoolitt/index_diff

Merged support of indexed part select

10 files changed, 272 insertions, 78 deletions

diff --git a/examples/bigfile.vhd b/examples/bigfile.vhd
index 3fc1d9d..a9624ba 100644
--- a/examples/bigfile.vhd
+++ b/examples/bigfile.vhd
@@ -100,7 +100,6 @@ architecture rtl of bigfile is
   signal q_g_zaq_in_cd : std_logic_vector(3 downto 0);
   signal q_g_style_vfr_dout : std_logic_vector(31 downto 0);
   signal q_g_unzq : std_logic_vector(3 downto 0);
-  -- i
   signal g_n_active : std_logic_vector(31 downto 0);
 
   -- inter
@@ -192,6 +191,8 @@ begin
   g_doutister_proc :
   process(reset, sysclk)
     variable g_dout_w0x0f_v : std_logic_vector(4 downto 0);
+    variable i : integer;
+    variable j : integer;
   begin
     if( reset /= '0' ) then
       g_t_klim_dout                  <= (others => '0');
@@ -227,7 +228,7 @@ begin
               -- set
               g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
             else
-              exit;
+              -- XXX not ready for exit;
             end if;
           --vnavigatoroff
           else
@@ -323,6 +324,7 @@ begin
  
   lpq_proc :
   process(reset, sysclk)
+    variable i : integer;
   begin
     if( reset /= '0' ) then
       q_g_zaq_in_cd      <= (others => '0');
@@ -383,6 +385,7 @@ begin
   -- also clear
   n_proc :
   process(reset, sysclk)
+    variable i : integer;
   begin
     if( reset /= '0' ) then
       g_n_vfr_dout <= (others => '0');
@@ -424,6 +427,7 @@ begin
   createwerth_vec_proc :
   process( g_n_r_bne_dout, g_e_n_r_dout)
     variable imod8, idiv8 : integer;
+    variable i : integer;
   begin
     for i in 0 to 31 loop
       imod8 := i mod 8;
@@ -451,6 +455,7 @@ begin
   
   create_g_ack_bne_proc :
   process( swe_ed,swe_lv,g_e_z_dout)
+    variable i : integer;
   begin
     for i in 0 to 31 loop
       if( g_e_z_dout(i) = '1') then
diff --git a/examples/dsp.vhd b/examples/dsp.vhd
index 7eda7c1..a762a4e 100644
--- a/examples/dsp.vhd
+++ b/examples/dsp.vhd
@@ -5,28 +5,37 @@ USE IEEE.numeric_std.all;
 
 entity dsp is generic(
   rst_val   : std_logic := '0';
-  thing_size: integer := 201;
-  bus_width : integer := 24);
+  thing_size: integer   := 51;
+  bus_width : integer   := 24);
     port(
       -- Inputs
       clk, rstn : in std_logic;
       en, start : in std_logic;
-      param : in std_logic_vector(7 downto 0);
-      addr : in std_logic_vector(2 downto 0);
-      din : in std_logic_vector(bus_width-1 downto 0);
-      we : in std_logic;
-      memdin : out std_logic_vector(13 downto 0);
+      param     : in std_logic_vector(7 downto 0);
+      addr      : in std_logic_vector(2 downto 0);
+      din       : in std_logic_vector(bus_width-1 downto 0);
+      we        : in std_logic;
+      memdin    : out std_logic_vector(13 downto 0);
       -- Outputs
-      dout : out std_logic_vector(bus_width-1 downto 0);
-      memaddr : out std_logic_vector(5 downto 0);
-      memdout : out std_logic_vector(13 downto 0)
+      dout      : out std_logic_vector(bus_width-1 downto 0);
+      memaddr   : out std_logic_vector(5 downto 0);
+      memdout   : out std_logic_vector(13 downto 0)
       );
 end;
 
 architecture rtl of dsp is
     signal foo : std_logic;
+    signal sr  : std_logic_vector(63 downto 0);
+    signal iparam : integer;
 begin
+    iparam <= to_integer(unsigned(param));
     process(clk) begin
-       dout <= std_logic_vector(to_unsigned(1,bus_width));
+       -- dout <= std_logic_vector(to_unsigned(1,bus_width));
+       if rising_edge(clk) then
+           if we = '1' then
+              sr <= sr(thing_size-bus_width-1 downto 0) & din;
+           end if;
+           dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width);
+       end if;
     end process;
 end rtl;
diff --git a/examples/for.vhd b/examples/for.vhd
index c18c2e3..71ff3a5 100644
--- a/examples/for.vhd
+++ b/examples/for.vhd
@@ -12,7 +12,7 @@ architecture rtl of forp is
 begin
   TIMERS :
   process(reset, sysclk)
-    variable timer_var : integer:= 0;
+    variable timer_var : integer; -- XXX unhandled := 0;
     variable a, i, j, k : integer;
     variable zz5 : std_logic_vector(31 downto 0);
     variable zz : std_logic_vector(511 downto 0);
diff --git a/examples/partselect.vhd b/examples/partselect.vhd
new file mode 100644
index 0000000..86dc073
--- /dev/null
+++ b/examples/partselect.vhd
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity partselect is
+   port(
+      clk_i : in std_logic
+   );
+end entity partselect;
+
+architecture rtl of partselect is
+   signal big_sig : std_logic_vector(31 downto 0);
+   signal lit_sig : std_logic_vector(0 to 31);
+   signal i       : integer:=8;
+begin
+
+   test_i: process(clk_i)
+      variable big_var : std_logic_vector(31 downto 0);
+      variable lit_var : std_logic_vector(0 to 31);
+      variable j       : integer; -- XXX not ready for :=8;
+   begin
+      if rising_edge(clk_i) then
+         big_sig(31 downto 24) <= big_sig(7 downto 0);
+         big_var(31 downto 24) := big_var(7 downto 0);
+         lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7);
+         lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0);
+         --
+         big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0);
+         big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0);
+      end if;
+   end process test_i;
+
+end architecture rtl;
diff --git a/src/def.h b/src/def.h
index cd51456..85acc95 100644
--- a/src/def.h
+++ b/src/def.h
@@ -54,6 +54,7 @@ typedef struct vrange {
   struct slist *nhi, *nlo; /* MAG index is a simple expression */
   slist *size_expr;        /* expression that calculates size (width) of this vrange */
   int    sizeval;          /* precalculated size value */
+  int    updown;           /* only used for indext part select case */
   struct slist *xhi, *xlo; /* array index range; 0,0 for normal scalars */
 } vrange;
 
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index b71c704..0e116ce 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -121,6 +121,40 @@ void sldump(int ind, slist *sl){
   }
 }
 
+size_t limlen(char *p, size_t l){
+  size_t r = strlen(p);
+  if (l < r) r = l;
+  return r;
+}
+
+char *sslprint(char *p, size_t l, slist *sl){
+  char *o = p;
+  if(sl){
+    assert(sl != sl->slst);
+    o = sslprint(o, l, sl->slst);
+    l = p+l-o;
+    switch(sl->type){
+    case tSLIST : case tOTHERS :
+      assert(sl != sl->data.sl);
+      o = sslprint(o, l, sl->data.sl);
+      break;
+    case tTXT :
+      strncpy(o, sl->data.txt, l);
+      o += limlen(sl->data.txt, l);
+      break;
+    case tVAL :
+      snprintf(o, l, "%d", sl->data.val);
+      o += strlen(o);
+      break;
+    case tPTXT :
+      strncpy(o, *(sl->data.ptxt), l);
+      o += limlen(*(sl->data.ptxt), l);
+      break;
+    }
+  }
+  return o;
+}
+
 void fslprint(FILE *fp,slist *sl){
   if(sl){
     assert(sl != sl->slst);
@@ -268,30 +302,36 @@ slist *addind(slist *sl){
   return sl;
 }
 
-slist *addpar(slist *sl, vrange *v){
+#define DEBUG_RANGE 0
+slist *addpar_snug(slist *sl, vrange *v){
+  if (DEBUG_RANGE) {
+    fprintf(stderr,"addpar_snug %d: ", v->sizeval);
+    fslprint(stderr, v->size_expr);
+    fprintf(stderr,"\n");
+  }
   if(v->nlo != NULL) {   /* indexes are simple expressions */
-    sl=addtxt(sl," [");
+    sl=addtxt(sl,"[");
     if(v->nhi != NULL){
       sl=addsl(sl,v->nhi);
-      sl=addtxt(sl,":");
+      if(v->updown) sl=addtxt(sl,v->updown==1 ? " +: " : " -: ");
+      else sl=addtxt(sl,":");
     }
-    sl=addsl(sl,v->nlo);
-    sl=addtxt(sl,"] ");
-  } else {
-    sl=addtxt(sl," ");
+    if(v->updown){
+      sl=addsl(sl,v->size_expr);
+      sl=addtxt(sl," + 1");
+    } else {
+      sl=addsl(sl,v->nlo);
+    }
+    sl=addtxt(sl,"]");
   }
   return sl;
 }
 
-slist *addpar_snug(slist *sl, vrange *v){
+slist *addpar(slist *sl, vrange *v){
+  sl=addtxt(sl," ");
   if(v->nlo != NULL) {   /* indexes are simple expressions */
-    sl=addtxt(sl,"[");
-    if(v->nhi != NULL){
-      sl=addsl(sl,v->nhi);
-      sl=addtxt(sl,":");
-    }
-    sl=addsl(sl,v->nlo);
-    sl=addtxt(sl,"]");
+    sl=addpar_snug(sl, v);
+    sl=addtxt(sl," ");
   }
   return sl;
 }
@@ -376,6 +416,57 @@ char *sbottom(slist *sl){
   return sl->data.txt;
 }
 
+/* kind of like strdup, but with specified len */
+char *strgrab(char*s, size_t len)
+{
+  char *r = malloc(len+1);
+  if (r) {
+    memcpy(r, s, len);
+    r[len] = 0;
+  }
+  return r;
+}
+
+/* s1 is the longer string, s2 is the shorter string */
+char *string_check_diff(char *s1, char *s2)
+{
+  size_t llen = strlen(s1);
+  size_t slen = strlen(s2);
+  char *rv=0;
+  if (memcmp(s1, s2, slen)==0) {
+    if (DEBUG_RANGE) fprintf(stderr, "first %lu chars match\n", slen);
+    if (llen>slen+3 && memcmp(s1+slen," + ",3)==0) {
+      if (DEBUG_RANGE) fprintf(stderr, "followed by valid \" + \"\n");
+      rv=strgrab(s1+slen+3,llen-slen-3);
+    }
+  } else if (memcmp(s1+llen-slen, s2, slen)==0) {
+    if (DEBUG_RANGE) fprintf(stderr, "last %lu chars match\n", slen);
+    if (llen>slen+3 && memcmp(s1+llen-slen-3," + ",3)==0) {
+      if (DEBUG_RANGE) fprintf(stderr, "preceded by valid \" + \"\n");
+      rv=strgrab(s1,llen-slen-3);
+    }
+  }
+  return rv;
+}
+
+/* Look for common beginning or end of a string,
+ * as needed for creating indexed part selects.
+ * updown key:  DOWNTO = -1, TO = 1 */
+char *slist_check_diff(slist *shi, slist *slo, int updown)
+{
+  char t1[200], t2[200];
+  char *diff = 0;
+  size_t t1len, t2len;
+  sslprint(t1, sizeof(t1), shi);  t1len = strlen(t1);
+  sslprint(t2, sizeof(t2), slo);  t2len = strlen(t2);
+  if (updown == -1 && t2len < t1len) {
+    diff = string_check_diff(t1, t2);
+  } else if (updown == 1 && t1len < t2len) {
+    diff = string_check_diff(t2, t1);
+  } /* I don't have sane test cases for the other possibilities */
+  return diff;
+}
+
 const char *inout_string(int type)
 {
   const char *name=NULL;
@@ -1106,10 +1197,26 @@ type        : BIT {
 
 /* using expr instead of simple_expr here makes the grammar ambiguous (why?) */
 vec_range : simple_expr updown simple_expr {
+              char *range_diff = 0;
               $$=new_vrange(tVRANGE);
               $$->nhi=$1->sl;
               $$->nlo=$3->sl;
               $$->sizeval = -1; /* undefined size */
+              $$->updown = 0; /* not relevant */
+              /* Here is where we may want to analyze the two expressions to
+               * see if they have a simple (possibly constant) difference.
+               * For now, here's an option to visualise their data structures.
+               */
+              if (DEBUG_RANGE) {
+                fprintf(stderr, "debug width hi: ");
+                fslprint(stderr, $$->nhi);
+                fprintf(stderr, "\n");
+                if (0) sldump(4, $$->nhi);
+                fprintf(stderr, "debug width lo: ");
+                fslprint(stderr, $$->nlo);
+                fprintf(stderr, "\n");
+                if (0) sldump(4, $$->nlo);
+              }
               /* calculate the width of this vrange */
               if ($1->op == 'n' && $3->op == 'n') {
                 if ($2==-1) { /* (nhi:natural downto nlo:natural) */
@@ -1117,6 +1224,10 @@ vec_range : simple_expr updown simple_expr {
                 } else {      /* (nhi:natural to     nlo:natural) */
                   $$->sizeval = $3->value - $1->value + 1;
                 }
+              } else if ((range_diff = slist_check_diff($$->nhi, $$->nlo, $2))) {
+                if (DEBUG_RANGE) fprintf(stderr, "difference: %s\n", range_diff);
+                $$->updown = $2;  /* triggers use of range_diff in addpar_snug */
+                $$->size_expr = addtxt(NULL, range_diff);
               } else {
                 /* make an expression to calculate the width of this vrange:
                  * create an expression that calculates:
@@ -1127,21 +1238,6 @@ vec_range : simple_expr updown simple_expr {
                 expdata *diff12  = xmalloc(sizeof(expdata));
                 expdata *plusone = xmalloc(sizeof(expdata));
                 expdata *finalexpr = xmalloc(sizeof(expdata));
-                /* Here is where we may want to analyze the two expressions to
-                 * see if they have a simple (possibly constant) difference.
-                 * For now, here's an option to visualise their data structures.
-                 */
-                if (0) {
-                  fprintf(stderr, "debug width hi ");
-                  fslprint(stderr, $$->nhi);
-                  fprintf(stderr, "\n");
-                  sldump(4, $$->nhi);
-                  fprintf(stderr, "debug width lo ");
-                  fslprint(stderr, $$->nlo);
-                  fprintf(stderr, "\n");
-                  sldump(4, $$->nlo);
-                  fprintf(stderr, "\n");
-                }
                 size_expr1->sl = addwrap("(",$1->sl,")");
                 size_expr2->sl = addwrap("(",$3->sl,")");
                 plusone->op='t';
@@ -1157,6 +1253,7 @@ vec_range : simple_expr updown simple_expr {
                 finalexpr->sl = addwrap("(",finalexpr->sl,")");
                 $$->size_expr = finalexpr->sl;
               }
+              if (DEBUG_RANGE) fprintf(stderr, "\n");
             }
           | simple_expr {
               $$=new_vrange(tSUBSCRIPT);
@@ -2233,6 +2330,9 @@ expr : signal {
        /* single argument type conversion function e.g. std_logic_vector(x) */
        $$ = addnest($3);
       }
+     | CONVFUNC_1 '(' expr ')' {
+       $$ = addnest($3);
+      }
      | CONVFUNC_2 '(' expr ',' expr ')' {
        /* two argument type conversion e.g. to_unsigned(x, 3) */
        $$ = addnest($3);
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index 36dfdb8..974dc55 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -91,7 +91,7 @@ reg [31:0] q2_g_zaq_in;
 reg [31:0] q3_g_zaq_in;
 reg [3:0] q_g_zaq_in_cd;
 reg [31:0] q_g_style_vfr_dout;
-reg [3:0] q_g_unzq;  // i
+reg [3:0] q_g_unzq;
 wire [31:0] g_n_active;  // inter
 wire [31:0] g_zaq_in_y;
 wire [31:0] g_zaq_in_y_no_dout;
@@ -135,8 +135,10 @@ wire [31:0] g_dout_i;
   // qaz
   assign g_zaq_in_rst_hold = g_style_main_reset_hold_dout;
   // Din 
-  always @(posedge reset, posedge sysclk) begin : P2
+  always @(posedge reset, posedge sysclk) begin : P5
     reg [4:0] g_dout_w0x0f_v;
+    reg [31:0] i;
+    reg [31:0] j;
 
     if((reset != 1'b0)) begin
       g_t_klim_dout <= {32{1'b0}};
@@ -175,7 +177,7 @@ wire [31:0] g_dout_i;
               g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b1};
             end
             else begin
-              disable;  //VHD2VL: add block name here
+              // XXX not ready for exit;
             end
             //vnavigatoroff
           end
@@ -185,7 +187,7 @@ wire [31:0] g_dout_i;
           //vnavigatoron
           case(g_dout_w0x0f_v)
           g_t_klim_w0x0f : begin
-            g_t_klim_dout <= din[i * 32 + 31:i * 32];
+            g_t_klim_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_t_u_w0x0f : begin
             // output klim
@@ -196,68 +198,68 @@ wire [31:0] g_dout_i;
             end
           end
           g_t_l_w0x0f : begin
-            g_t_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_t_hhh_l_w0x0f : begin
-            g_t_hhh_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_hhh_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_t_jkl_sink_l_w0x0f : begin
-            g_t_jkl_sink_l_dout <= din[i * 32 + 31:i * 32];
+            g_t_jkl_sink_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_secondary_t_l_w0x0f : begin
-            g_secondary_t_l_dout <= din[i * 32 + 31:i * 32];
+            g_secondary_t_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_style_c_l_w0x0f : begin
-            g_style_c_l_dout[3:0] <= din[3 + i * 32:i * 32];
+            g_style_c_l_dout[3:0] <= din[3 + i * 32 -: 3 + 1];
           end
           g_e_z_w0x0f : begin
-            g_e_z_dout <= din[i * 32 + 31:i * 32];
+            g_e_z_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_n_both_qbars_l_w0x0f : begin
-            g_n_both_qbars_l_dout <= din[i * 32 + 31:i * 32];
+            g_n_both_qbars_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_style_vfr_w0x0f : begin
             // read-only register
           end
           g_style_klim_w0x0f : begin
-            g_style_klim_dout <= din[i * 32 + 31:i * 32];
+            g_style_klim_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_unklimed_style_vfr_w0x0f : begin
             // read-only register
           end
           g_style_t_y_w0x0f : begin
-            g_style_t_y_dout <= din[i * 32 + 31:i * 32];
+            g_style_t_y_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_n_l_w0x0f : begin
-            g_n_l_dout <= din[i * 32 + 31:i * 32];
+            g_n_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_n_vfr_w0x0f : begin
             // writes
           end
           g_e_n_r_w0x0f : begin
-            g_e_n_r_dout <= din[i * 32 + 31:i * 32];
+            g_e_n_r_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_n_r_bne_w0x0f : begin
             g_n_r_bne_dout <= din[i * 32];
           end
           g_n_div_rebeq_w0x0f : begin
-            g_n_div_rebeq_dout <= din[i * 32 + 31:i * 32] | g_n_div_rebeq_dout;
+            g_n_div_rebeq_dout <= din[i * 32 + 31 -: 31 + 1] | g_n_div_rebeq_dout;
             // a '1' writes
           end
           g_alu_l_w0x0f : begin
-            g_alu_l_dout <= din[i * 32 + 31:i * 32];
+            g_alu_l_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_t_qaz_mult_low_w0x0f : begin
-            g_t_qaz_mult_low_dout <= din[i * 32 + 31:i * 32];
+            g_t_qaz_mult_low_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           g_t_qaz_mult_high_w0x0f : begin
-            g_t_qaz_mult_high_dout <= din[i * 32 + 31:i * 32];
+            g_t_qaz_mult_high_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           gwerthernal_style_u_w0x0f : begin
-            gwerthernal_style_u_dout <= din[i * 32 + 31:i * 32];
+            gwerthernal_style_u_dout <= din[i * 32 + 31 -: 31 + 1];
           end
           gwerthernal_style_l_w0x0f : begin
-            gwerthernal_style_l_dout <= din[i * 32 + 31:i * 32];
+            gwerthernal_style_l_dout <= din[i * 32 + 31 -: 31 + 1];
             //vnavigatoroff                                                          
           end
           default : begin
@@ -294,7 +296,9 @@ wire [31:0] g_dout_i;
   assign g_sys_in_i = {g_zaq_in_y_no_dout[31:4],(g_style_c_l_dout[3:0] & q_g_zaq_in_cd) | ( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])};
   assign g_sys_in_ii = (g_sys_in_i &  ~gwerthernal_style_l_dout) | (gwerthernal_style_u_dout & gwerthernal_style_l_dout);
   assign g_sys_in = g_sys_in_ii;
-  always @(posedge reset, posedge sysclk) begin
+  always @(posedge reset, posedge sysclk) begin : P4
+    reg [31:0] i;
+
     if((reset != 1'b0)) begin
       q_g_zaq_in_cd <= {4{1'b0}};
       q_g_unzq <= {4{1'b1}};
@@ -347,7 +351,9 @@ wire [31:0] g_dout_i;
   assign g_n_active = ((q_g_style_vfr_dout &  ~g_style_vfr_dout) | ( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout)) & g_n_l_dout;
   // check for lqq active and set lqq vfr register
   // also clear
-  always @(posedge reset, posedge sysclk) begin
+  always @(posedge reset, posedge sysclk) begin : P3
+    reg [31:0] i;
+
     if((reset != 1'b0)) begin
       g_n_vfr_dout <= {32{1'b0}};
       gwerth <= {32{1'b0}};
@@ -389,23 +395,24 @@ wire [31:0] g_dout_i;
 
   //--
   // Create the Lqq
-  always @(g_n_r_bne_dout, g_e_n_r_dout) begin : P1
+  always @(g_n_r_bne_dout, g_e_n_r_dout) begin : P2
     reg [31:0] imod8, idiv8;
+    reg [31:0] i;
 
     for (i=0; i <= 31; i = i + 1) begin
       imod8 = i % 8;
       idiv8 = i / 8;
       if((g_n_r_bne_dout == 1'b0)) begin
         // non-unique
-        g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
+        g_vector[8 * i + 7 -: 7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1];
       end
       else begin
         // unique
         if((imod8 == 0)) begin
-          g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
+          g_vector[8 * i + 7 -: 7 + 1] <= g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1];
         end
         else begin
-          g_vector[8 * i + 7:8 * i] <= (g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8]) + (imod8);
+          g_vector[8 * i + 7 -: 7 + 1] <= (g_e_n_r_dout[8 * idiv8 + 7 -: 7 + 1]) + (imod8);
         end
       end
     end
@@ -414,7 +421,9 @@ wire [31:0] g_dout_i;
   //--
   // Qaz
   assign g_noop = g_n_div_rebeq_dout;
-  always @(swe_ed, swe_lv, g_e_z_dout) begin
+  always @(swe_ed, swe_lv, g_e_z_dout) begin : P1
+    reg [31:0] i;
+
     for (i=0; i <= 31; i = i + 1) begin
       if((g_e_z_dout[i] == 1'b1)) begin
         swe_qaz1[i] <= swe_ed;
diff --git a/translated_examples/dsp.v b/translated_examples/dsp.v
index 52474d3..557ca0d 100644
--- a/translated_examples/dsp.v
+++ b/translated_examples/dsp.v
@@ -17,7 +17,7 @@ output wire [13:0] memdout
 );
 
 parameter rst_val=1'b0;
-parameter [31:0] thing_size=201;
+parameter [31:0] thing_size=51;
 parameter [31:0] bus_width=24;
 // Inputs
 // Outputs
@@ -25,9 +25,16 @@ parameter [31:0] bus_width=24;
 
 
 wire foo;
-
-  always @(clk) begin
-    dout <= 1;
+reg [63:0] sr;
+wire [31:0] iparam;
+
+  assign iparam = param;
+  always @(posedge clk) begin
+      // dout <= std_logic_vector(to_unsigned(1,bus_width));
+    if(we == 1'b1) begin
+      sr <= {sr[thing_size - bus_width - 1:0],din};
+    end
+    dout <= sr[iparam * bus_width + bus_width - 1 -: bus_width - 1 + 1];
   end
 
 
diff --git a/translated_examples/for.v b/translated_examples/for.v
index 0c00762..ce31bc7 100644
--- a/translated_examples/for.v
+++ b/translated_examples/for.v
@@ -12,7 +12,8 @@ reg selection;
 reg [6:0] egg_timer;
 
   always @(posedge reset, posedge sysclk) begin : P1
-    reg [31:0] timer_var = 0;
+    reg [31:0] timer_var;
+  // XXX unhandled := 0;
     reg [31:0] a, i, j, k;
     reg [31:0] zz5;
     reg [511:0] zz;
@@ -28,7 +29,7 @@ reg [6:0] egg_timer;
       for (i=0; i <= j * k; i = i + 1) begin
         a = a + i;
         for (k=a - 9; k >=  -14; k = k - 1) begin
-          zz5 = zz[31 + k:k];
+          zz5 = zz[31 + k -: 31 + 1];
         end
         // k
       end
diff --git a/translated_examples/partselect.v b/translated_examples/partselect.v
new file mode 100644
index 0000000..11ec901
--- /dev/null
+++ b/translated_examples/partselect.v
@@ -0,0 +1,30 @@
+// no timescale needed
+
+module partselect(
+input wire clk_i
+);
+
+
+
+
+reg [31:0] big_sig;
+reg [0:31] lit_sig;
+wire [31:0] i = 8;
+
+  always @(posedge clk_i) begin : P1
+    reg [31:0] big_var;
+    reg [0:31] lit_var;
+    reg [31:0] j;
+  // XXX not ready for :=8;
+
+    big_sig[31:24] <= big_sig[7:0];
+    big_var[31:24] = big_var[7:0];
+    lit_sig[i * 3 +: 7 + 1] <= lit_sig[0:7];
+    lit_var[j * 3 +: 8 + 1] = lit_var[j * 0 +: 8 + 1];
+    //
+    big_sig[i * 3 + 8 -: 8 + 1] <= big_sig[8:0];
+    big_var[j * 3 + 8 -: 8 + 1] = big_var[j * 0 + 8 -: 8 + 1];
+  end
+
+
+endmodule