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author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-11-26 11:08:38 -0300 |
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committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-11-26 11:08:38 -0300 |
commit | a9c964453724ad820673fd6d07794f5dd2b602cb (patch) | |
tree | 8a8650be9df4300bc877514a19b63c739d06d485 | |
parent | 32fe8418c53a7a3341c7e66d947fbc368a2eb4b9 (diff) | |
download | vhdl2vl-a9c964453724ad820673fd6d07794f5dd2b602cb.tar.gz vhdl2vl-a9c964453724ad820673fd6d07794f5dd2b602cb.zip |
Renamed generic to withselect
-rw-r--r-- | examples/withselect.vhd (renamed from examples/generic.vhd) | 7 | ||||
-rw-r--r-- | translated_examples/withselect.v (renamed from translated_examples/generic.v) | 2 |
2 files changed, 5 insertions, 4 deletions
diff --git a/examples/generic.vhd b/examples/withselect.vhd index 10c2d0e..48f6f0a 100644 --- a/examples/generic.vhd +++ b/examples/withselect.vhd @@ -1,7 +1,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; -entity generic1 is +entity withselect is generic( dog_width : std_logic_vector(7 downto 0) := "10101100"; bus_width : integer := 32 @@ -9,8 +9,9 @@ entity generic1 is port( reset, sysclk : in std_logic; a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) ); -end generic1; -architecture rtl of generic1 is +end withselect; + +architecture rtl of withselect is signal foo : std_logic_vector(1+1 downto 0); signal code,code1: std_logic_vector(9 downto 0); signal egg : std_logic_vector(324 to 401); diff --git a/translated_examples/generic.v b/translated_examples/withselect.v index e523dfc..2461a0a 100644 --- a/translated_examples/generic.v +++ b/translated_examples/withselect.v @@ -1,6 +1,6 @@ // no timescale needed -module generic1( +module withselect( input wire reset, input wire sysclk, input wire [bus_width:0] a, |