Renamed while to whileloop

2 files changed, 4 insertions, 5 deletions

diff --git a/examples/while.vhd b/examples/whileloop.vhd
index 5d2ee9e..44793e3 100644
--- a/examples/while.vhd
+++ b/examples/whileloop.vhd
@@ -2,16 +2,15 @@ library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-entity whilep is port(
+entity whileloop is port(
   A : in integer;
   Z : out std_logic_vector(3 downto 0)
 );
-end whilep;
+end whileloop;
 
-architecture rtl of whilep is
+architecture rtl of whileloop is
 begin
 
-
 process (A)
     variable I : integer range 0 to 4;
 begin
diff --git a/translated_examples/while.v b/translated_examples/whileloop.v
index 0464707..d3778fb 100644
--- a/translated_examples/while.v
+++ b/translated_examples/whileloop.v
@@ -1,6 +1,6 @@
 // no timescale needed
 
-module whilep(
+module whileloop(
 input wire [31:0] A,
 output reg [3:0] Z
 );