From a9c964453724ad820673fd6d07794f5dd2b602cb Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Sun, 26 Nov 2017 11:08:38 -0300 Subject: Renamed generic to withselect --- examples/generic.vhd | 33 ------------------------------- examples/withselect.vhd | 34 ++++++++++++++++++++++++++++++++ translated_examples/generic.v | 42 ---------------------------------------- translated_examples/withselect.v | 42 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 75 deletions(-) delete mode 100644 examples/generic.vhd create mode 100644 examples/withselect.vhd delete mode 100644 translated_examples/generic.v create mode 100644 translated_examples/withselect.v diff --git a/examples/generic.vhd b/examples/generic.vhd deleted file mode 100644 index 10c2d0e..0000000 --- a/examples/generic.vhd +++ /dev/null @@ -1,33 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; - -entity generic1 is - generic( - dog_width : std_logic_vector(7 downto 0) := "10101100"; - bus_width : integer := 32 - ); - port( reset, sysclk : in std_logic; - a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) - ); -end generic1; -architecture rtl of generic1 is - signal foo : std_logic_vector(1+1 downto 0); - signal code,code1: std_logic_vector(9 downto 0); - signal egg : std_logic_vector(324 to 401); - signal baz : std_logic_vector(bus_width*3-1 to bus_width*4); - signal complex : std_logic_vector(31 downto 0); -begin - -- Example of with statement - with foo(2 downto 0) select - code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110", - "11100010" when "101", - (others => '1') when "010", - (others => '0') when "011", - std_logic_vector(unsigned(a) + unsigned(b)) when others; - code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); - - foo <= (others => '0'); - egg <= (others => '0'); - baz <= (others => '1'); - complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; -end rtl; diff --git a/examples/withselect.vhd b/examples/withselect.vhd new file mode 100644 index 0000000..48f6f0a --- /dev/null +++ b/examples/withselect.vhd @@ -0,0 +1,34 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all, IEEE.numeric_std.all; + +entity withselect is + generic( + dog_width : std_logic_vector(7 downto 0) := "10101100"; + bus_width : integer := 32 + ); + port( reset, sysclk : in std_logic; + a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0) + ); +end withselect; + +architecture rtl of withselect is + signal foo : std_logic_vector(1+1 downto 0); + signal code,code1: std_logic_vector(9 downto 0); + signal egg : std_logic_vector(324 to 401); + signal baz : std_logic_vector(bus_width*3-1 to bus_width*4); + signal complex : std_logic_vector(31 downto 0); +begin + -- Example of with statement + with foo(2 downto 0) select + code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110", + "11100010" when "101", + (others => '1') when "010", + (others => '0') when "011", + std_logic_vector(unsigned(a) + unsigned(b)) when others; + code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6)); + + foo <= (others => '0'); + egg <= (others => '0'); + baz <= (others => '1'); + complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001"; +end rtl; diff --git a/translated_examples/generic.v b/translated_examples/generic.v deleted file mode 100644 index e523dfc..0000000 --- a/translated_examples/generic.v +++ /dev/null @@ -1,42 +0,0 @@ -// no timescale needed - -module generic1( -input wire reset, -input wire sysclk, -input wire [bus_width:0] a, -input wire [bus_width:0] b, -input wire [bus_width:0] enf, -input wire [bus_width:0] load, -input wire [bus_width:0] qtd, -input wire [bus_width:0] base -); - -parameter [7:0] dog_width=8'b10101100; -parameter [31:0] bus_width=32; - - - -wire [1 + 1:0] foo; -reg [9:0] code; wire [9:0] code1; -wire [324:401] egg; -wire [bus_width * 3 - 1:bus_width * 4] baz; -wire [31:0] complex; - - // Example of with statement - always @(*) begin - case(foo[2:0]) - 3'b000,3'b110 : code[9:2] <= {3'b110,egg[325:329]}; - 3'b101 : code[9:2] <= 8'b11100010; - 3'b010 : code[9:2] <= {8{1'b1}}; - 3'b011 : code[9:2] <= {8{1'b0}}; - default : code[9:2] <= (a) + (b); - endcase - end - - assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); - assign foo = {(((1 + 1))-((0))+1){1'b0}}; - assign egg = {78{1'b0}}; - assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}}; - assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001}; - -endmodule diff --git a/translated_examples/withselect.v b/translated_examples/withselect.v new file mode 100644 index 0000000..2461a0a --- /dev/null +++ b/translated_examples/withselect.v @@ -0,0 +1,42 @@ +// no timescale needed + +module withselect( +input wire reset, +input wire sysclk, +input wire [bus_width:0] a, +input wire [bus_width:0] b, +input wire [bus_width:0] enf, +input wire [bus_width:0] load, +input wire [bus_width:0] qtd, +input wire [bus_width:0] base +); + +parameter [7:0] dog_width=8'b10101100; +parameter [31:0] bus_width=32; + + + +wire [1 + 1:0] foo; +reg [9:0] code; wire [9:0] code1; +wire [324:401] egg; +wire [bus_width * 3 - 1:bus_width * 4] baz; +wire [31:0] complex; + + // Example of with statement + always @(*) begin + case(foo[2:0]) + 3'b000,3'b110 : code[9:2] <= {3'b110,egg[325:329]}; + 3'b101 : code[9:2] <= 8'b11100010; + 3'b010 : code[9:2] <= {8{1'b1}}; + 3'b011 : code[9:2] <= {8{1'b0}}; + default : code[9:2] <= (a) + (b); + endcase + end + + assign code1[1:0] = a[6:5] ^ ({a[4],b[6]}); + assign foo = {(((1 + 1))-((0))+1){1'b0}}; + assign egg = {78{1'b0}}; + assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}}; + assign complex = {enf,3'b110 * (load),qtd[3:0],base,5'b11001}; + +endmodule -- cgit v1.2.1