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* opal-api: Reserve 2 OPAL API calls for future OpenCAPI LPC useAndrew Donnellan2019-04-091-2/+4
| | | | | | | | | | | | OpenCAPI Lowest Point of Coherency (LPC) memory is going to require some extra OPAL calls to set up NPU BARs. These calls will most likely be called OPAL_NPU_LPC_ALLOC and OPAL_NPU_LPC_RELEASE, we're not quite ready to upstream that code yet though. Reserve 171 and 172 for this purpose. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* include/imc: Trace IMC Macro definitionsAnju T Sudhakar2019-03-281-0/+1
| | | | | | | | | | Add macros needed for Trace mode enablement of IMC(In-Memory Collection Counters). These macros are used to identify the trace node in the device-tree and to make appropriate scom calls to enable trace-mode in the hardware. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* xive: Add calls to save/restore the queues and VPs HW stateCédric Le Goater2019-03-281-3/+4
| | | | | | | | | | | | | | | | | To be able to support migration of guests using the XIVE native exploitation mode, (where the queue is effectively owned by the guest), KVM needs to be able to save and restore the HW-modified fields of the queue, such as the current queue producer pointer and generation bit, and to retrieve the modified thread context registers of the VP from the NVT structure : the VP interrupt pending bits. However, there is no need to set back the NVT structure on P9. P10 should be the same. Based on previous work from BenH. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal/hmi: set a flag to inform OS that TOD/TB has failed.Mahesh Salgaonkar2019-03-051-0/+1
| | | | | | | | | | Set a flag to indicate OS about TOD/TB failure as part of new opal_handle_hmi2 handler. This flag then can be used by OS to make sure functions depending on TB value (e.g. udelay()) are aware of TB not ticking. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Add support for relaxed-ordering modeReza Arbab2018-08-061-1/+3
| | | | | | | | | | | | | | | | | | Some device drivers support out of order access to GPU memory. This does not affect the CPU view of memory but it does affect the GPU view of memory. It should only be enabled if the GPU driver has requested it. Add OPAL APIs allowing the driver to query relaxed ordering state or request it to be set for a device. Current hardware only allows relaxed ordering to be enabled per PCIe root port. So the code here doesn't enable relaxed ordering until it has been explicitly requested for every device on the port. Signed-off-by: Alistair Popple <alistair@popple.id.au> [arbab@linux.ibm.com: Rebase/refactor original changes] Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* NX: Add NX coprocessor init opal callHaren Myneni2018-06-181-1/+2
| | | | | | | | | | | | | | | | | | The read offset (4:11) in Receive FIFO control register is incremented by FIFO size whenever CRB read by NX. But the index in RxFIFO has to match with the corresponding entry in FIFO maintained by VAS in kernel. VAS entry is reset to 0 when opening the receive window during driver initialization. So when NX842 is reloaded or in kexec boot, possibility of mismatch between RxFIFO control register and VAS entries in kernel. It could cause CRB failure / timeout from NX. This patch adds nx_coproc_init opal call for kernel to initialize readOffset (4:11) and Queued (15:23) in RxFIFO control register. Fixes: 3b3c5962f432 ("NX: Add P9 NX support for 842 compression engine") CC: stable # v5.8+ Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal/hmi: Add a new opal_handle_hmi2 that returns direct info to LinuxBenjamin Herrenschmidt2018-04-171-0/+8
| | | | | | | | | It returns a 64-bit flags mask currently set to provide info about which timer facilities were lost, and whether an event was generated. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Reserve OPAL API number for opal_handle_hmi2 function.Mahesh Salgaonkar2018-03-141-1/+2
| | | | | | Requested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: set PBCQ Tunnel BAR for tunneled operationsPhilippe Bergheaud2018-03-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI tunneled operations (atomics and as_notify) that are initiated by devices. A subset of the tunneled operations require a response, that must be sent back from the host to the device. For example, an atomic compare and swap will return the compare status, as swap will only performed in case of success. Similarly, as_notify reports if the target thread has been woken up or not, because the operation may fail. To enable tunneled operations, a device driver must tell the host where it expects tunneled operation responses, by setting the PBCQ Tunnel BAR Response register with a specific value within the range of its BARs. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also operate in PCI mode, a new API is required to set the PBCQ Tunnel BAR Response register, without switching to CAPI mode. This patch provides two new OPAL calls to get/set the PBCQ Tunnel BAR Response register. Note: as there is only one PBCQ Tunnel BAR register, shared between all the devices connected to the same PHB, only one of these devices will be able to use tunneled operations, at any time. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2-opencapi: Add OpenCAPI OPAL API callsFrederic Barrat2018-03-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add three OPAL API calls that are required by the ocxl driver. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The NPU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-api: Re-jig OPAL API numbers because OpenCAPI kernel mergeStewart Smith2018-02-211-3/+6
| | | | | | | | | | 74d656d219b98ef3b96f92439337aa6392a7577d added OPAL APIs to kernel (and this commit is now in Linus' tree) that hadn't yet made their way to OPAL. Also, be slightly grumbly about it. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* npu2/opal-api: move npu2 checkstop defines to npu2-regs.hStewart Smith2018-02-211-98/+0
| | | | | | | | These aren't API. Fixes: b57a5380aa489fa877b2d619225aea2602f20dca Reported-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensor-groups: occ: Add support to disable/enable sensor groupShilpasri G Bhat2018-02-211-2/+3
| | | | | | | | | | This patch adds a new opal call to enable/disable a sensor group. This call is used to select the sensor groups that needs to be copied to main memory by OCC at runtime. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [stewart: rebase and bump OPAL API number] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: Support reading u64 sensor valuesShilpasri G Bhat2018-02-211-1/+2
| | | | | | | | | | | | | This patch adds support to read u64 sensor values. This also adds changes to the core and the backend implementation code to make this API as the base call. Host can use this new API to read sensors upto 64bits. This adds a list to store the pointer to the kernel u32 buffer, for older kernels making async sensor u32 reads. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/npu2: Implement logging HMI actionsBalbir Singh2018-02-081-0/+98
| | | | | | | | | Log HMI errors as step 1. OS will need to deduce and interpret the HMI event. Signed-off-by: Balbir Singh <bsingharora@gmail.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-prd: occ: Add support for runtime OCC load/start in ZZShilpasri G Bhat2017-12-141-0/+2
| | | | | | | | | | | | | This patch adds support to handle OCC load/start event from FSP/PRD. During IPL we send a success directly to FSP without invoking any HBRT load routines on recieving OCC load mbox message from FSP. At runtime we forward this event to host opal-prd. This patch provides support for invoking OCC load/start HBRT routines like load_pm_complex() and start_pm_complex() from opal-prd. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-prd: Add support for runtime OCC reset in ZZShilpasri G Bhat2017-12-141-0/+11
| | | | | | | | | | This patch handles OCC_RESET runtime events in host opal-prd and also provides support for calling 'hostinterface->wakeup()' which is required for doing the reset operation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Acked-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: Add support for quiescing OPALNicholas Piggin2017-12-031-1/+8
| | | | | | | | | | | | | | | | Quiescing is ensuring all host controlled CPUs (except the current one) are out of OPAL and prevented from entering. This can be use in debug and shutdown paths, particularly with system reset sequences. This patch adds per-CPU entry and exit tracking for OPAL calls, and adds logic to "hold" or "reject" at entry time, if OPAL is quiesced. An OPAL call is added, to expose the functionality to Linux, where it can be used for shutdown, kexec, and before generating sreset IPIs for debugging (so the debug code does not recurse into OPAL). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Define API for single-escalation VP modeBenjamin Herrenschmidt2017-11-281-0/+1
| | | | | | | | | | | This mode allows all queues of a VP to use the same escalation interrupt, at the cost of losing priority 7. This adds the definition and documentation of the API, the implementation will come next. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Add OPAL_REINIT_CPUS_TM_SUSPEND_DISABLEDMichael Ellerman2017-10-161-0/+2
| | | | | | | | | | | | | Add a new CPU reinit flag, "TM Suspend Disabled", which requests that CPUs be configured so that TM (Transactional Memory) suspend mode is disabled. Currently this always fails, because skiboot has no way to query the state. A future hostboot change will add a mechanism for skiboot to determine the status and return an appropriate error code. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Enable PCI peer-to-peerFrederic Barrat2017-08-041-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: occ: Add support to clear sensor groupsShilpasri G Bhat2017-07-281-1/+2
| | | | | | | | | | Adds a generic API to clear sensor groups. OCC inband sensor groups such as CSM, Profiler and Job Scheduler can be cleared using this API. It will clear the min/max of all sensors belonging to OCC sensor groups. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* psr: occ: Add support to change power-shifting-ratioShilpasri G Bhat2017-07-281-1/+3
| | | | | | | | | | | Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Documentation enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* powercap: occ: Add a generic powercap frameworkShilpasri G Bhat2017-07-281-1/+3
| | | | | | | | | | | This patch adds a generic powercap framework and exports OCC powercap sensors using which system powercap can be set inband through OPAL-OCC command-response interface. Documentation for powercap enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Add support for OPAL-OCC command/response interfaceShilpasri G Bhat2017-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a shared memory based command/response interface between OCC and OPAL. In HOMER, there is an OPAL command buffer and an OCC response buffer which is used to send inband commands to OCC. The OPAL-OCC command/response sequence is as follows: 1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready' bit in OPAL command flag are set to zero. If yes then proceed with below steps to send a command to OCC. 2. Write the command value, request ID and command specific data to the OPAL command buffer. 3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command flag to indicate command is ready. 4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit is set by OPAL. If the bit is set then OCC will set the 'OCC Progress' bit. 5. OCC will process the command and write the response to the OCC response buffer and set the 'Rsp Ready' bit in the response flag and sends an interrupt. 8. OPAL will receive the interrupt and queue the response to the host. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Fix comment around OPAL_IMC_COUNTERS_ enumMadhavan Srinivasan2017-07-171-1/+1
| | | | | | Fixes: 7801be0fcf2a2 ('skiboot: Add opal calls to init/start/stop IMC devices) Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Add opal calls to init/start/stop IMC devicesAnju T Sudhakar2017-06-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | Add new opal calls to init, start and stop the IMC nest/core units. To initialize the core IMC counters, it takes a physical address per core as an input and writes that address to PDBAR[14:50] bits. It initializes the htm_mode and event_mask, where it selects the time interval at which the counter values must be posted to the given memory location and enables the counters to start running by setting the appropriate bits. To disable/enable the nest IMC counters (stop or resume counting), writes into "command" field of the nest control block in the reserve memory location. To disable/enable the core IMC counters (stop or resume counting), writes into appropriate bits of htm_mode to disable the counters. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt rather than hardcode IMC prefix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Support setting HID[RADIX] and set it by default on P9Benjamin Herrenschmidt2017-06-261-0/+9
| | | | | | | | | | | | | | | | | This adds new opal_reinit_cpus() flags to setup radix or hash mode in HID[8] on POWER9. By default HID[8] will be set. On P9 DD1.0, Linux will change it as needed. On P9 DD2.0 hash works in radix mode (radix is really "dual" mode) so KVM won't break and existing kernels will work. Newer kernels built for hash will call this to clear the HID bit and thus get the full size of the TLB as an optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Enable capi mode for PHB4Christophe Lombard2017-06-191-0/+1
| | | | | | | | | | | | | | | | Enable the Coherently attached processor interface. The PHB is used as a CAPI interface. CAPI Adapters can be connected to either PEC0 or PEC2. Single port CAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port Adapter can be only connected to PEC2 CAPP0 attached to PHB0(PEC0 - single port) CAPP1 attached to PHB3(PEC2 - single or dual port) As we did for PHB3, a new specific file 'phb4-capp.h' is created to contain the CAPP register definitions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SBE: Add passthrough command supportVasant Hegde2017-06-081-0/+4
| | | | | | | | | | | | SBE sends passthrough command. We have to capture this interrupt and send event to HBRT via opal-prd (user space daemon). This patch adds minimal SBE code to capture SBE interrupt and send event to opal-prd. Next patch will add opal-prd (user space) support. CC: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-prd: Add firmware_request & firmware_notify implementationsJeremy Kerr2017-06-061-0/+16
| | | | | | | | | This change adds the implementation of firmware_request() and firmware_notify(). To do this, we need to add a message queue, so that we can properly handle out-of-order messages coming from firmware. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Implement diag dataRussell Currey2017-04-191-2/+69
| | | | | | | | | Implement PHB4 diagnostic data, similar to PHB3. There are a few registers that have changed, but everything is largely the same. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org>
* npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple2017-03-301-1/+4
| | | | | | | | | | | Adds three OPAL calls for interacting with NPU2 devices: opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar. These are used to setup and configure address translation services (ATS) for a process/partition on a given NVLink2 device. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt2017-03-161-0/+7
| | | | | | | | For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* System reset IPI facility and Mambo implementationNicholas Piggin2017-03-071-1/+2
| | | | | | | | | | | | | Add an opal call OPAL_SIGNAL_SYSTEM_RESET which allows system reset exceptions to be raised on other CPUs and act as an NMI IPI. There is an initial simple Mambo implementation, but allowances are made for a more complex hardware implementation. This API is based on the POWER8 implementation from Alistair Popple. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: minor RST fix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add some dump facilityBenjamin Herrenschmidt2017-02-231-2/+12
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Reserve OPAL API numbers for XIVEStewart Smith2017-01-161-1/+5
| | | | | | (requested by benh) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add *any chip* for allocating interruptsBenjamin Herrenschmidt2017-01-051-0/+5
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add support for EOIs via OPALBenjamin Herrenschmidt2017-01-051-0/+1
| | | | | | | | | | | opal_xive_eoi() can perform EOIs in XIVE exploitation mode as well as XICS emulation mode. Add a per-interrupt flag requiring the OS to use the OPAL call instead of ESB access. This is meant to be used as a broken HW workaround Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Work around broken LSI control on P9 DD1Benjamin Herrenschmidt2017-01-051-0/+1
| | | | | | | | | Exposes a new flag to the OS to indicate that OPAL calls are needed for masking and unmasking and forward the calls to the source so that PHB4 can do the right thing Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Export opal_xive_reset() arguments in OPAL APIBenjamin Herrenschmidt2017-01-051-0/+9
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Handle bad ESB offsets in PHB4 DD1Benjamin Herrenschmidt2017-01-051-0/+1
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: OPAL API updateBenjamin Herrenschmidt2017-01-051-1/+35
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* platform: add OPAL_REBOOT_FULL_IPL reboot typeAndrew Donnellan2016-12-231-0/+1
| | | | | | | | | | There may be circumstances in which a user wants to force a full IPL reboot rather than using fast reboot. Add a new reboot type, OPAL_REBOOT_FULL_IPL, that disables fast reboot. On platforms which don't support fast reboot, this will be equivalent to a normal reboot. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Set PSSCR value for idle statesShilpasri G Bhat2016-12-131-0/+15
| | | | | | | | | | | | | | | | | | | | PSSCR(Processor Stop Status and Control Register) is an SPR whose contents control the operation of stop instruction. Currently in DT, the value of PSSCR only included RL(Requested Level) for each idle state. This patch adds MTL(Maximum Transistion Level), TR(Transistion Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle state in the PSSCR configuration. It also adds new idle states stop0_lite, stop1_lite and stop2_lite which are no state loss versions of stop0, stop1 and stop2 respectively. The lite variant has EC and ESL bits of PSSCR set to 0. The thread entering a lite variant of stop state will not lose any state and will wakeup at next instruction following stop if MSR.EE=0 or at the corresponding interrupt handler if MSR.EE=1. This will reduce the exit latency of the idle state and hardware will not allocate the thread resources to other threads while in power saving mode. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ/prd/opal-prd: Queue OCC_RESET event message to host in OpenPOWERShilpasri G Bhat2016-09-261-0/+1
| | | | | | | | | | | | | | | | | During an OCC reset cycle the system is forced to Psafe pstate. When OCC becomes active, the system has to be restored to its last pstate as requested by host. So host needs to be notified of OCC_RESET event or else system will continue to remian in Psafe state until host requests a new pstate after the OCC reset cycle. This patch defines 'OPAL_PRD_MSG_TYPE_OCC_RESET_NOTIFY' to notify OPAL when opal-prd issues OCC reset. OPAL will queue OCC_RESET message to host when it receives opal_prd_msg of type '*_OCC_RESET_NOTIFY'. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* centaur: Mark centaur offline after 10 consecutive access errorsBenjamin Herrenschmidt2016-09-131-0/+1
| | | | | | | | This avoids spamming the logs when the centaur is dead and PRD constantly tries to access it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Map all HMER status codes to OPAL errorsBenjamin Herrenschmidt2016-09-131-0/+7
| | | | | | | | | | Instead of mapping them to just 3 different codes, define an OPAL error code for all known HMER error status, as different recovery path might be needed at the call site, and it allows for more informative logging. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/cpu.c: Add OPAL call to setup Nest MMUAlistair Popple2016-09-061-1/+2
| | | | | | | | | | | | | | | POWER9 has an off core MMU called the Nest MMU which allows other units within a chip to perform address translations. The context and setup for translations is handled by the requesting agents, however the Nest MMU does need to know where in system memory the page tables are located. This patch adds a call to setup the Nest MMU page table pointer on a per-chip basis. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add infrastructure for pointer validation.Balbir Singh2016-08-121-0/+3
| | | | | | | | | | | | | | If the kernel called an OPAL API with vmalloc'd address or any other address range in real mode, we would hit a problem with aliasing. Since the top 4 bits are ignored in real mode, pointers from 0xc.. and 0xd.. (and other ranges) could collide and lead to hard to solve bugs. This patch adds the infrastructure for pointer validation and a simple test case for testing the API Signed-off-by: Balbir Singh <bsingharora@gmail.com> [stewart@linux.vnet.ibm.com: move function to opal-internal.h rather than opal-api.h] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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