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This adds support for the HW SerIRQ deserializer of the P8 LPC
bridge which is properly wired up on Naples. It also adds support
for detecting and reporting LPC error interrupts on all P8s.
On most platforms (Rhesus is the exception here due to the way it
lets Linux handle the UART interrupts directly), we modify the
device-tree to properly represent the LPC controller as a cascaded
interrupt-controller and the "interrupts" property of LPC devices
to contain the actual LPC interrupt number for the device.
We add a mechanism for drivers to register specific LPC interrupts,
and a "workaround" for pre-Naples P8 which platforms can use to call
all of them for when the external FPGA based deserializer is used.
There's also a callback on LPC resets which isn't used yet, we need
a bit more work on the general LPC error handling, but it can be
done a separate patches.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The bits in the control register are mostly write-1-to-clear, so
the rmw sequences in bt_setmask() and bt_clearmask() don't work.
Additionally, H_BUSY is weird as it's a write-1-to-toggle, so let's
write a "safe" function that sets it to the desired state based on
its previous state. (We can optimize that further later).
Also enable interrupt operations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The initial implementation of the ipmi stack was still tightly coupled
with the backend (in this case bt). This patch refactors the ipmi code
to use a generic backend device.
The core ipmi messaging functionality and the implementation of
specific commands has also been split into different files.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The original implementation of the bt and ipmi layers required the bt,
ipmi and message data to be allocated separately. This is sub-optimal
as it could cause excessive memory fragmentation. This patch fixes the
problem by adding a function to the bt layer to allocate space for
both the required data and bt/ipmi message.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This patch adds a basic IPMI layer to the sapphire core and support
for a BT IPMI interface as found on the Aspeed BMC of the Palmetto
platform
[ Changed the compatible property -- BenH ]
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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