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* Remove POWER9N DD1 supportNicholas Piggin2019-01-251-51/+0
| | | | | | | | This is not a shipping product and is no longer supported by Linux or other firmware components. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Print verbose info on errors onlyAkshay Adiga2019-01-251-2/+7
| | | | | | | | | | Change print level from debug to warning for reporting bad EC_PPM_SPECIAL_WKUP_* scom values. To reduce cluttering in the log print only on error. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Remove Idle state support tor Power8 DD1Akshay Adiga2019-01-251-50/+0
| | | | | | | | Removing init routines required for Power8 DD1, but was enabled for all Power8 DD versions. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* slw: Fix trivial typo in debug messageAndrew Donnellan2018-06-271-1/+1
| | | | | | | s/goint/going/ Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Quieten console output on bootStewart Smith2018-06-051-1/+1
| | | | | | | | | | | We print out a whole bunch of things on boot, most of which aren't interesting, so we should *not* print them instead. Printing things like what CPUs we found and what PCI devices we found *are* useful, so continue to do that. But we don't need to splat out a bunch of things that are always going to be true. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Remove stop1_lite and stop2_liteAkshay Adiga2018-05-241-28/+8
| | | | | | | | | | | | | | | | | | | | | | stop1_lite has been removed since it adds no additional benefit over stop0_lite. stop2_lite has been removed since currently it adds minimal benefit over stop2. However, the benefit is eclipsed by the time required to ungate the clocks Moreover, Lite states don't give up the SMT resources, can potentially have a performance impact on sibling threads. Since current OSs (Linux) aren't smart enough to make good decisions with these stop states, we're (temporarly) removing them from what we expose to the OS, the idea being to bring them back in a new DT representation so that only an OS that knows what to do will do things with them. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> [stewart: add to explanation] Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* cpu: Do an isync after setting LPCRBenjamin Herrenschmidt2018-05-241-0/+2
| | | | | | | | This is required by the architecture and the implementations, I've observed failures to wake up on big cores without this. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Update default stop-state-disable mask to cut only stop11Vaidyanathan Srinivasan2018-05-091-1/+1
| | | | | | | | | | | | | | | Stability improvements in microcode for stop4/stop5 are available in upstream hcode images. Stop4 and stop5 can be safely enabled by default. Use ~0xE0000000 to cut all but stop0,1,2 in case there are any issues with stop4/5. example: nvram -p ibm,skiboot --update-config opal-stop-state-disable-mask=0x1FFFFFFF Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Fix mambo boot to use stop statesAnton Blanchard2018-05-021-0/+1
| | | | | | | | | | | | After commit 35c66b8ce5a2 ("SLW: Move MAMBO simulator checks to slw_init"), mambo boot no longer calls add_cpu_idle_state_properties() and as such we never enable stop states. After adding the call back, we get more testing coverage as well as faster mambo SMT boots. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: quieten 'Configuring self-restore' for DARN,NCU_SPEC_BAR and HRMORStewart Smith2018-05-011-1/+1
| | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Move P8 timer code to separate fileVasant Hegde2018-04-301-183/+2
| | | | | | | | | | | | | Lets move P8 timer support code from slw.c to sbe-p8.c (as suggested by BenH). There is a difference between timer support in P8 and P9. Hence I think it makes sense to name it as sbe-p8.c. Note that this is pure code movement and renaming functions/variables. No functionality changes. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/slw: Don't assert on a unknown chipOliver O'Halloran2018-04-291-2/+10
| | | | | | | | | | | | | | | | | For some reason skiboot populates nodes in /cpus/ for the cores on chips that are deconfigured. As a result Linux includes the threads of those cores in it's set of possible CPUs in the system and attempts to set the SPR values that should be used when waking a thread from a deep sleep state. However, in the case where we have deconfigured chip we don't create a xscom node for that chip and as a result we don't have a proc_chip structure for that chip either. In turn, this results in an assertion failure when calling opal_slw_set_reg() since it expects the chip structure to exist. Fix this up and print an error instead. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Disable stop states from OPALStewart Smith2018-04-111-0/+23
| | | | | | | | | | | | | | | | | | | | | On ZZ, stop4,5,11 are enabled for PHYP, even though doing so may cause problems with OPAL due to bugs in hcode. For other platforms, this isn't so much of an issue as we can just control stop states by the MRW. However the rebuild-the-world approach to changing values there is a bit annoying if you just want to rule out a specific stop state from being problematic. Provide an nvram option to override what's disabled in OPAL. The OPAL mask is currently ~0xE0000000 (i.e. all but stop 0,1,2) You can set an NVRAM override with: nvram -p ibm,skiboot --update-config opal-stop-state-disable-mask=0xFFFFFFF This nvram override will disable *all* stop states. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Revert "NPU2 HMIs: dump out a *LOT* of npu2 registers for debugging"Stewart Smith2018-03-271-2/+2
| | | | | | | | | | | | | This reverts commit fbdc91e693fc3103f7e2a65054ed32bfb26a2e17. We don't need this as we need to do it a different way, with a explicit set of registers as otherwise we trip other random FIR bits and everything becomes even more terrible. I suggest alcohol. Cc: stable Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Increase stop4-5 residency by 10xAkshay Adiga2018-03-221-2/+2
| | | | | | | | | | | | | | | Using DGEMM benchmark we observed there was a drop of 5-9% throughput with and without stop4/5. In this benchmark the GPU waits on the cpu to wakeup and provide the subsequent data block to compute. The wakup latency accumulates over the run and shows up as a performance drop. Linux enters stop4/5 more aggressively for its wakeup latency. Increasing the residency from 1ms to 10ms makes the performance drop <1% Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Acked-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Tested-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* NPU2 HMIs: dump out a *LOT* of npu2 registers for debuggingStewart Smith2018-02-281-2/+2
| | | | | | | | | | This is not the way we want to end up doing this. This is a hack to make folk happy and not require crondump to debug nvidia/npu2 issues. Cc: stable Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: fix running in mamboStewart Smith2018-01-151-1/+3
| | | | | Fixes: 35c66b8ce5a27ad3312806e8bde9148a5e5b5df8 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SCOM restore for DARN and XIVEAkshay Adiga2018-01-141-2/+4
| | | | | | | | | | While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Call p9_stop_api only if deep_states are enabledAkshay Adiga2018-01-141-0/+9
| | | | | | | | | | | All init time p9_stop_api calls have been isolated to slw_late_init. If p9_stop_api fails, then the deep states can be excluded from device tree. For p9_stop_api called after device-tree for cpuidle is created , has_deep_states will be used to check if this call is even required. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Detect if deep states are enabledAkshay Adiga2018-01-141-1/+15
| | | | | | | | Patch adds a global variable which indicates if the deep states are enabled through stop-enabled-bits. Only applies to POWER9. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Move MAMBO simulator checks to slw_initAkshay Adiga2018-01-141-7/+2
| | | | | | | Move MAMBO simulator checks to slw_init. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Use wakeup_engine state to handle errors in wakeup engineAkshay Adiga2018-01-141-24/+14
| | | | | | | | | | | Patch introduces wakeup_engine_state which replaces a bool has_wakeup_engine. wakeup_engine_state can have 3 states : - WAKEUP_ENGINE_PRESENT : When everything is good. - WAKEUP_ENGINE_NOT_PRESENT : When wakeup_engine is not correctly detected. - WAKEUP_ENGINE_FAILED : If any operation on wakeup_engine failed. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Call slw_late_init_p{8, 9} only when has_wakeup_engine is setAkshay Adiga2018-01-141-14/+37
| | | | | | | | | | | | Patch adds the following changes : - Moves slw image sanity check to a seperate function called slw_image_check_p{8,9}() - Move has_wakeup_engine to global scope, so that it can be set by other functions - Code which uses wakeup_engine will only be called if sanity check passes. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Split init functionsAkshay Adiga2018-01-141-32/+43
| | | | | | | | | This patch seperates code which deals with wakeup_engine from one which doesn't. Init functions for power8 and power9 are split into chip_init and late_init. slw_late_init_p?() contains wakeup_engine related code. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Delay cpuidle device-tree creationAkshay Adiga2018-01-141-0/+1
| | | | | | | | | Create cpuidle device-tree after slw_init(), so that we can stop the deeper states from being added , when wakeup engine is not present or failed. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Add idle state stop5 for DD2.0 and aboveAkshay Adiga2017-12-181-0/+16
| | | | | | | Adding stop5 idle state with rough residency and latency numbers. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle POWER9 power management implementationNicholas Piggin2017-09-281-1/+1
| | | | | | | | | | | | Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Removing timebase related flags for stop4Akshay Adiga2017-09-191-2/+2
| | | | | | | | | When a core enters stop4, it does not loose decrementer and time base. Hence removing flags OPAL_PM_DEC_STOP and OPAL_PM_TIMEBASE_STOP. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Allow deep states if homer address is knownAkshay Adiga2017-09-191-6/+17
| | | | | | | | | | | | | | Use a common variable has_wakeup_engine instead of has_slw to tell if the a) SLW image is populated in case of power8 b) CME image is populated in case of power9 Currently we expect CME to be loaded if homer address is known ( except for simulators) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Configure self-restore for HRMORAkshay Adiga2017-09-191-0/+29
| | | | | | | | | | Make a stop api call using libpore to restore HRMOR register. HRMOR needs to be cleared so that when thread exits stop, they arrives at linux system_reset vector (0x100). Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Add opal_slw_set_reg support for power9Akshay Adiga2017-09-191-20/+40
| | | | | | | | | This OPAL call is made from Linux to OPAL to configure values in various SPRs after wakeup from a deep idle state. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Revert "hw/slw.c: Offline code still uses p8 bits"Stewart Smith2017-09-191-3/+0
| | | | | | This reverts commit 0a2710381f34e6b4c03cff1fa76bc1b74f280ecd. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw.c: Offline code still uses p8 bitsBalbir Singh2017-09-151-0/+3
| | | | | | | | | | | | | | | | | I'm seeing an infinite loop while hot unplugging a CPU. This is a workaround till we do the right things for p9. May be a candidate for backporting The messages I see in an infinite loop are: [ 740.250192896,3] LIBPORE: Core ID = 20 is not within valid range of [0;15] [ 740.250230176,3] SLW: Failed to set spr for CPU 51 When trying to hotunplug core id 20. For now the patch just skips calling p8_pore* on p9 machines. Signed-off-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* idle: disable stop*_lite POWER9 idle states for Mambo platformNicholas Piggin2017-09-041-1/+110
| | | | | | | | | | | | | | Mambo prior to Mambo.7.8.21 had a bug where the stop idle instruction with PSSCR[ESL]=PSSCR[EC]=0 would resume with MSR set as though it had taken a system reset interrupt. Linux currently executes this instruction with MSR already set that way, so the problem went unnoticed. A proposed patch to Linux changes that, and causes the idle code to crash. Work around this by disabling lite stop states for the mambo platform for now. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* idle: user context state loss flags fix for stop statesNicholas Piggin2017-09-041-4/+4
| | | | | | | | | | | | | The "lite" stop variants with PSSCR[ESL]=PSSCR[EC]=1 do not lose user context, while the non-lite variants do (ESL: enable state loss). Some of the POWER9 idle states had these wrong. These are not used by Linux yet. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Modify the power9 stop0_lite latency & residencyGautham R. Shenoy2017-08-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently skiboot exposes the exit-latency for stop0_lite as 200ns and the target-residency to be 2us. However, the kernel cpu-idle infrastructure rounds up the latency to microseconds and lists the stop0_lite latency as 0us, putting it on par with snooze state. As a result, when the predicted latency is small (< 1us), cpuidle will select stop0_lite instead of snooze. The difference between these states is that snooze doesn't require an interrupt to exit from the state, but stop0_lite does. And the value 200ns doesn't include the interrupt latency. This shows up in the context_switch2 benchmark (http://ozlabs.org/~anton/junkcode/context_switch2.c) where the number of context switches per second with the stop0_lite disabled is found to be roughly 30% more than with stop0_lite enabled. =============================================================================== x latency_200ns_residency_2us + latency_200ns_residency_2us_stop0_lite_disabled N Min Max Median Avg Stddev x 100 222784 473466 294510 302295.26 45380.6 + 100 205316 609420 385198 396338.72 78135.648 Difference at 99.0% confidence 94043.5 +/- 23276.2 31.1098% +/- 7.69983% (Student's t, pooled s = 63892.8) =============================================================================== This can be correlated with the number of times cpuidle enters stop0_lite compared to snooze. =================================================================== latency=200ns, residency=2us stop0_lite enabled. * snooze usage = 7 * stop0 lite usage = 3200324 * stop1 lite usage = 6 stop0_lite disabled * snooze usage: 287846 * stop0_lite usage: 0 * stop1_lite usage: 0 ================================================================== Hence, bump up the exit latency of stop0_lite to 1us. Since the target residency is chosen to be 10 times the exit latency, set the target residency to 10us. With these values, we see a 50% improvement in the number of context switches: ===================================================================== x latency_200ns_residency_2us + latency_1us_residency_10us N Min Max Median Avg Stddev x 100 222784 473466 294510 302295.26 45380.6 + 100 281790 710784 514878 510224.62 85163.252 Difference at 99.0% confidence 207929 +/- 24858.3 68.7835% +/- 8.22319% (Student's t, pooled s = 68235.5) ===================================================================== The cpuidle usage statistics show that we choose stop0_lite less often in such cases. latency = 1us, residency = 10us stop0_lite enabled * snooze usage = 536808 * stop0 lite usage = 3 * stop1 lite usage = 7 Reported-by: Anton Blanchard <anton@samba.org> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Big log level reduction...Benjamin Herrenschmidt2017-06-261-2/+2
| | | | | | | | | | | | | 90% of what we print isn't useful to a normal user. This dramatically reduces the amount of messages printed by OPAL in normal circumstances. We still need to add a way to bump the log level at boot based on a BMC scratch register or some HDAT property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Ensure P9 DD1 workarounds apply only to NimbusMichael Neuling2017-06-191-4/+5
| | | | | | | | | | | The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus will be DD1 but don't need these same workarounds. This patch ensures the P9 DD1 workarounds only apply to Nimbus. It also renames some things to make clear what's what. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pore: Always use libporeOliver O'Halloran2017-05-101-25/+0
| | | | | | | | | In the days of yore libpore was closed source and people wanted the option to not use it. That's no longer the case so lets ditch all the #ifdef crap. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SLW: Add init for power9 power managementAkshay Adiga2017-03-301-7/+51
| | | | | | | | | | | This patch adds new function to init core for power9 power management. SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each core during init. (This init are not required for MAMBO) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Define stop idle states for P9 DD1Shilpasri G Bhat2017-03-231-4/+57
| | | | | | | | | Only stop[0,1]_lite idle states are supported in DD1. And stop1 with ESL=EC=1 is used for CPU hotplug in DD1. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: fix NOTICE/WARNING of idle states found/not-foundStewart Smith2017-03-161-2/+2
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: fix possible NULL dereferenceStewart Smith2017-03-021-2/+8
| | | | | | Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Print enabled stop statesMichael Neuling2017-02-221-0/+2
| | | | | | | | | | | | | | On boot, print the enabled stop states. Output looks like: [ 25.045201661,5] SLW: Enabling: stop0_lite [ 25.045205017,5] SLW: Enabling: stop0 [ 25.045206549,5] SLW: Enabling: stop1_lite [ 25.045208320,5] SLW: Enabling: stop1 [ 25.045209738,5] SLW: Enabling: stop2_lite [ 25.045211467,5] SLW: Enabling: stop2 Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Fix parsing of supported STOP statesShilpasri G Bhat2017-02-071-2/+4
| | | | | | | | | | | Bits[0-15] are used to indicate the supported STOP states in "ibm,enabled-stop-levels" DT property and STOP0 is starting from Bit0. This patch fixes the parsing to read the appropriate bits. Fixes: c3ea33f173ec ("hw/slw: only enable supported STOP states") Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: fix typo in slw dump commentJeremy Kerr2017-02-031-1/+1
| | | | | | | | | | | | We have an typo in a @fwts-advice field, which means it's carried through to the generated fwts olog data. This change fixes the typo so that the advice output from fwts is correct. CC: Deb McLemore <debmc@linux.vnet.ibm.com> Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: only enable supported STOP statesOliver O'Halloran2017-01-161-0/+14
| | | | | | | | | This patch adds parsing the ibm,enabled-stop-levels field when building the /ibm,opal/power-mgt/ node so that only the STOP levels that have been advertised by firmware are used. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/slw: use dt_new_check()Oliver O'Halloran2017-01-161-3/+2
| | | | | | | | | | On P9 systems the /ibm,opal/power-mgt/ node may be created by the HDAT parser before reaching add_cpu_idle_state_properties(). This is fine, but it needs to be handled. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Set PSSCR value for idle statesShilpasri G Bhat2016-12-131-14/+78
| | | | | | | | | | | | | | | | | | | | PSSCR(Processor Stop Status and Control Register) is an SPR whose contents control the operation of stop instruction. Currently in DT, the value of PSSCR only included RL(Requested Level) for each idle state. This patch adds MTL(Maximum Transistion Level), TR(Transistion Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle state in the PSSCR configuration. It also adds new idle states stop0_lite, stop1_lite and stop2_lite which are no state loss versions of stop0, stop1 and stop2 respectively. The lite variant has EC and ESL bits of PSSCR set to 0. The thread entering a lite variant of stop state will not lose any state and will wakeup at next instruction following stop if MSR.EE=0 or at the corresponding interrupt handler if MSR.EE=1. This will reduce the exit latency of the idle state and hardware will not allocate the thread resources to other threads while in power saving mode. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: do SLW timer testing while holding xscom lockStewart Smith2016-11-241-3/+9
| | | | | | | | | | | We add some routines that let a caller get the xscom lock once and then do a bunch of xscoms while holding it. In some situations without this, it could take long enough to get the xscom lock that the 1ms timeout would expire and we'd falsely think the SLW timer didn't work when in fact it did. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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