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* hw/phb3/naples: Disable D-statesAlexey Kardashevskiy2019-02-201-0/+29
| | | | | | | | | | | | | | | Putting "Mellanox Technologies MT27700 Family [ConnectX-4] [15b3:1013]" (more precisely, the second of 2 its PCI functions, no matter in what order) into the D3 state causes EEH with the "PCT timeout" error. This has been noticed on garrison machines only and firestones do not seem to have this issue. This disables D-states changing for devices on root buses on Naples by installing a config space access filter (copied from PHB4). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-By: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal: Deprecate reading the PHB statusAlexey Kardashevskiy2019-02-181-8/+2
| | | | | | | | | | | | | | | | | The OPAL_PCI_EEH_FREEZE_STATUS call takes a bunch of parameters, one of them is @phb_status. It is defined as __be64* and always NULL in the current Linux upstream but if anyone ever decides to read that status, then the PHB3's handler will assume it is struct OpalIoPhb3ErrorData* (which is a lot bigger than 8 bytes) and zero it causing the stack corruption; p7ioc-phb has the same issue. This removes @phb_status from all eeh_freeze_status() hooks and moves the error message from PHB4 to the affected OPAL handlers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-By: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* sparse: Make tree 'constant is so big' warning cleanStewart Smith2019-01-181-122/+122
| | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* interrupts: Create an "interrupts" property in the OPAL nodeBenjamin Herrenschmidt2018-04-111-1/+1
| | | | | | | | | | | | Deprecate the old "opal-interrupts", it's still there, but the new property follows the standard and allow us to specify whether an interrupt is level or edge sensitive. Similarly create "interrupt-names" whose content is identical to "opal-interrupts-names". Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb*: Remove the state field in the various phb structuresOliver O'Halloran2018-03-221-15/+12
| | | | | | | | | | | | | | | | We've been carting around this field since the original p7ioc-phb code. As far as I can tell we never actually use it for anything other than checking if the PHB has been marked as broken or not. The _FENCED state is set in a few places, but we never use it in favour of just checking the MMIO register. This patch just replaces it with a boolean that indicates if the PHB has been marked as broken and removes the giant, mostly wrong, comment explaining it's usage that is copied and pasted into each phb header file. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/phb4/p7ioc: Document supported TCE sizes in DTRussell Currey2018-02-201-0/+5
| | | | | | | | | Add a new property, "ibm,supported-tce-sizes", to advertise to Linux how big the available TCE sizes are. Each value is a bit shift, from smallest to largest. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Silence a useless warningBenjamin Herrenschmidt2017-06-261-1/+1
| | | | | | | | | PHB's don't have base location codes on non-FSP systems and it's normal. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Move IO VPD preload out to a common placeBenjamin Herrenschmidt2017-06-261-10/+0
| | | | | | | | | | | | The code is duplicated between phb3 and phb4 for no reason Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> # Conflicts: # core/init.c # hw/phb3.c Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Handle HMI eventsChristophe Lombard2017-06-191-0/+35
| | | | | | | | | | | | Find the CAPP on the chip associated with the HMI event for PHB4. The recovery mode (re-initialization of the capp, resume of functional operations) is only available with P9 DD2. A new patch will be provided to support this feature. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Load capp microcodeChristophe Lombard2017-06-191-192/+13
| | | | | | | | | | | CAPP microcode flash download and CAPP upload for PHB4. A new file 'capp.c' is created to receive common capp code for PHB3 and PHB4. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Move phb3 capp registers to specialized filesChristophe Lombard2017-06-191-0/+1
| | | | | | | | | | | | | The definitions of the CAPP registers for PHB3 are moved in a specific file. The updated file capp.h will be used for the common functionalities about the CAPP for PHB3 and PHB4. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Externalize capp timebase synchronizationChristophe Lombard2017-06-191-1/+2
| | | | | | | | | | | | | Externalize the chiptod code. this code will be common for PHB3 and PHB4. The reference to the structure PHB3 is remove and new arguments appear due to specific address registers. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Use cached vendor/device IDs in phb3_check_device_quirks()Gavin Shan2017-06-151-19/+20
| | | | | | | | | | This uses the cached vendor/device IDs in phb3_check_device_quirks(). Also, to give the code and comment a cleaup. No logical changes are introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Make handling of config filters genericBenjamin Herrenschmidt2017-06-061-26/+4
| | | | | | | Move phb3_pcicfg_filter() to pci.c, rename it to pci_handle_cfg_filters() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Turn the link speed hack into a cfg filterBenjamin Herrenschmidt2017-06-061-10/+25
| | | | | | | Rather than special casing it openly. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3+iov: Fixup support for config space filtersBenjamin Herrenschmidt2017-06-061-15/+19
| | | | | | | | | | | The filter should be called before the HW access and its return value control whether to perform the access or not Also fix the pci-iov.c return values to match accordingly otherwise this breaks SR-IOV Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Add bitmap to know if a pci device has cfg reg filtersBenjamin Herrenschmidt2017-06-061-7/+2
| | | | | | | | This avoids doing a search through the list of all devices on every config space access to every device under a PHB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Rename pci_slot_op poll to run_smMichael Neuling2017-05-311-2/+2
| | | | | | | | | | | | | | | This renames the "poll" op to "run_sm" (short for run state machine). I think this is a better name since the function does a bunch of things like reseting the slot. Also it avoids confusion with the "poll_link" op which does something different (and can even be called from run_sm). No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Describe PHB diag data size in device treeRussell Currey2017-05-011-0/+3
| | | | | | | | | | | | | | | | | Linux hardcodes the PHB diag data buffer at (as of this commit) 8192 bytes. This has been enough for P7IOC and PHB3, but the 512 PEs of PHB4 pushes the diag data blob over this size. Rather than just increasing the hardcoded size in Linux, provide the size of the diag data blob in the device tree so that the OS can dynamically allocate as much as it needs. This both enables more space for PHB4 and less wasted memory for P7IOC and PHB3. P7IOC communicates both hub and PHB data using this buffer, so when setting the size, use whichever struct is largest. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Enable ECRC on endpointsGavin Shan2017-03-311-24/+2
| | | | | | | | | | | | As the ECRC is updated properly on root port, we needn't care the setting on endpoints. This reverts commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch"), meaning ECRC is always enabled on endpoints. Reported-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Adjust ECRC on root port dynamicallyGavin Shan2017-03-311-11/+63
| | | | | | | | | | | | | | | | | | | | | | | | | The issue was reported by Mark: the Samsung NVMe adapter is lost when it's connected to PMC 8546 PCIe switch, until ECRC is disabled on the root port. Actually, we found similar issue prevously when Broadcom adapter is connected to same part of PCIe switch and it was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch"). Unfortunately, the commit doesn't fix the Samsung NVMe adapter lost issue. This fixes the issues by disable ECRC generation/check on root port when PMC 8546 PCIe switch ports are found. This can be extended for other PCIe switches or endpoints in future: Each PHB maintains the count of PCI devices (PMC 8546 PCIe switch ports currently) which require to disable ECRC on root port. The ECRC functionality is enabled when first PMC 8546 switch port is probed and disabled when last PMC 8546 switch port is destroyed (in PCI hot remove scenario). Except PHB's reinitialization after complete reset, the ECRC on root port is untouched. Reported-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Add phb->ops->device_removeGavin Shan2017-03-311-0/+1
| | | | | | | | | | This adds another PHB callback (device_remove()), corresponding to device_init(). With it, the PHB3 layer can receive notification upon PCI topology changes. This functionality will be used by the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Locate AER capability position if necessaryGavin Shan2017-03-311-6/+9
| | | | | | | | | | | | phb3_init_rc_cfg() can be called when the PHB is initialized or reinitialized after complete reset. In the later case, we needn't locate the AER capability position again and the cached position can be used as we do for PCIe capability. So several CPU cycles can be saved. The error message is shortened and meaningless comment is dropped. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3/4: Set max link speed via nvramMichael Neuling2017-03-291-3/+14
| | | | | | | | | | | | | This adds an nvram parameter pcie-max-link-speed to configure the max speed of the pcie link. This can be set from the petitboot prompt using: nvram -p ibm,skiboot --update-config pcie-max-link-speed=4 This takes preference over anything set in the device tree and is global to all PHBs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: add host sync notifier to trigger creset/CAPP disable on kexecAndrew Donnellan2017-03-201-0/+40
| | | | | | | | | | | | | | | | | | | | To support kexec in Linux, we need to trigger a creset to disable CAPP mode on each PHB that has been attached to a CAPP. Add a host sync notifier, phb3_host_sync_reset(), that will be triggered by the opal_sync_host_reboot() call that Linux makes when "shutting down" a powernv system (this includes bringing the system down to prepare it for kexec). This notifier will trigger a creset only on PHBs that need it, and will poll regularly until the creset completes. This approach is somewhat hacky, as it's somewhat of an abuse of the host sync notifier system (IMHO), but it seems the most obvious way to ensure that the reset/CAPP disable occurs that will work with old kernel versions and not require additional support on the kernel side. Suggested-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: disable CAPI mode during complete resetAndrew Donnellan2017-03-201-5/+136
| | | | | | | | | | | | | | | | | | | | When fast rebooting or kexec-ing a system with a PHB in CAPI mode, we need to return the PHB to regular PCIe mode. In order to do this, we have to reset a bunch of registers to their pre-CAPI-mode state. However, doing this while there is traffic going over the PCI link is dangerous and will generally cause a checkstop. As such, we want to do this while the PHB is fenced. Conveniently, during a complete reset we force a PHB fence, so this is a good opportunity to disable CAPI mode. When doing a complete reset, if the PHB is in CAPI mode, execute a sequence of SCOMs to reset PHB-related registers back to their regular, PCIe mode values. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Apply config register filter after HW changeGavin Shan2017-02-161-3/+3
| | | | | | | | | | | | | | | The PCI config register is applied before the HW register is changed. It won't work when this mechanism is used to capture the change to SRIOV capability in subsequent patch. This moves the logic around so that the filter is applied after HW register is changed. Currently, it's used to cache bridge's pref window base/length. The code change shouldn't affect that. So no functional changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Initialize AER capability in PCI coreGavin Shan2017-02-161-16/+3
| | | | | | | | | | | | | | | | Currently, AER capability is initialized in phb_ops->device_init() which is called after the device is instantiated by PCI core, or reinitializing the device after reset in EEH recovery path. It means we are maintaining similar sets of codes for P7IOC, PHB3 and PHB4. This moves the logic initializing AER capability from P7IOC, PHB3 and PHB4 to PCI core, thus the duplicated codes can be dropped. No functional changes introduced by this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Lock the PHB on set_xive callbacksBenjamin Herrenschmidt2016-12-221-0/+8
| | | | | | | | | | Those are called by the interrupts core and thus skip the locking implicit in the PCI opal calls. However IODA table access can be racy, so make sure we lock the PHB. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* tree-wide: use dt_add_property_u64s() where we canOliver O'Halloran2016-12-211-4/+1
| | | | | | | | | | | | A few places (mostly old code) were using: add_property_cells(hi32(number), lo32(number)); This patch converts them to use the helper rather than doing it manually. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Always print PHB and PE numbers as hexadecimalRussell Currey2016-12-141-17/+17
| | | | | | | | | | | PHB and PE numbers are sometimes printed as decimal and sometimes as hexadecimal, which is confusing. Standardise on hexadecimal. This is especially useful now that PHB numbers in Linux always match their OPAL ID. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: fix error handling in complete resetAndrew Donnellan2016-12-131-2/+1
| | | | | | | | | | | | | | | During a complete reset, when we get a timeout waiting for pending transaction in state PHB3_STATE_CRESET_WAIT_CQ, we mark the PHB as permanently broken. Set the state to PHB3_STATE_FENCED so that the kernel can retry the complete reset. Reported-by: Pradipta Ghosh <pradghos@in.ibm.com> Suggested-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Trick to allow control of the PCIe link width and speedBenjamin Herrenschmidt2016-12-081-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements a hook inside OPAL that catches 16 and 32 bit writes to the link status register of the PHB. It allows you to write a new speed or a new width, and OPAL will then cause the PHB to renegociate. Example: First read the link status on PHB4: setpci -s 0004:00:00.0 0x5a.w a103 It's at x16 Gen3 speed (8GT/s) bits 0x0ff0 are the width and 0x000f the speed. The width can be 1 to 16 and the speed 1 to 3 (2.5, 5 and 8GT/s) Then try to bring it down to 1x Gen1 : setpci -s 0004:00:00.0 0x5a.w=0xa011 Observe the result in the PHB: / # lspci -s 0004:00:00.0 -vv 0004:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode]) .../... LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+ And in the device: / # lspci -s 0004:01:00.0 -vv .../... LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Remove obsoleted PCI slot pfreset() operationGavin Shan2016-10-241-16/+15
| | | | | | | | | | | PCI slot pfreset() operation is obsoleted as nobody uses it. This removes it and the related PCI slot states. No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Override root slot's prepare_link_change() with PHB'sGavin Shan2016-10-171-0/+8
| | | | | | | | | | | For PCI slot behind root port, its prepare_link_change() should be same to PHB's. Otherwise, the UTL events cannot be masked when the slot is reseted, leading to EEH error because of UTL link-down event. Cc: stable # 5.3.0+ Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Disable surprise link down event on PCI slotsGavin Shan2016-10-171-8/+49
| | | | | | | | | | This masks surprise link down event on RC or downtream ports if the PCI slots behind them support PCI surprise hotplug. The event should be handled by PCI hotplug driver instead of EEH subsystem. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Avoid hot resets at boot timeRussell Currey2016-10-121-2/+2
| | | | | | | | | | | | | | | | | | | In the PCI post-fundamental reset code, a hot reset is performed at the end. This is causing issues at boot time as a reset signal is being sent downstream before the links are up, which is causing issues on adapters behind switches. No errors result in skiboot, but the adapters are not usable in Linux as a result. Hot resets also occur in the FSP platform-specific code for conventional PCI slots, which could cause issues. This patch fixes some adapters not being configurable in Linux on some systems. The issue was not present in skiboot 5.2.x. Cc: stable # 5.3.x Signed-off-by: Russell Currey <ruscur@russell.cc> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Disable ECRC on Broadcom adapter behind PMC switchGavin Shan2016-10-111-2/+24
| | | | | | | | | | | | | | | | | The ECRC generation and check can't be enabled on Broadcom's NIC (14e4:168a) when it seats behind PMC PCIe switch downstream port (11f8:8546). Otherwise, the NIC's config space can not be accessed and returns 0xFF's on read because of EEH error even after the error is cleared. The issue is reported from Firestone. This disables ECRC generation and check on Broadcom's NIC when it seats behind PMC PCIe switch downstream port. With this applied, the NIC can be detected successfully. Reported-by: Li Meng <shlimeng@cn.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: add description of device workaround is for] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Revert "hw/phb3.c: adjust offset to run CAPP containers"Stewart Smith2016-10-111-22/+2
| | | | | | | This reverts commit cf39c2a7dd1a2ee9b19a5490f7fa25690b8e8ae3. Fixes: cf39c2a7dd1a2ee9b19a5490f7fa25690b8e8ae3 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Revert "hw/phb3.c: preload the whole CAPP partition"Stewart Smith2016-10-111-2/+2
| | | | | | | | | We should use the API properly. This reverts commit 0657bccb778cbe71fc8c00879826ca0217b7010d. Fixes: 0657bccb778cbe71fc8c00879826ca0217b7010d Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3.c: adjust offset to run CAPP containersClaudio Carvalho2016-10-101-2/+22
| | | | | | | This adjusts the CAPP header offset if CAPP is a secure boot container. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3.c: preload the whole CAPP partitionClaudio Carvalho2016-10-101-2/+2
| | | | | | | | | | This change preloads the whole CAPP partition. We decided to build a container for the whole CAPP lid as opposed to have one for the TOC and one for each subpartition. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Improve PCI config register filterGavin Shan2016-09-021-6/+8
| | | | | | | | | | | | | | | | This improves PCI config register filter so that it can be reused by PCI virtual device in subsequent patch: * First argument to pci_cfg_reg_func() is changed to "void *". It allows to accept variable data types including PCI virtual device in future. * Return value from pci_cfg_reg_func() to be used by PCI virtual device in future. * Shortened name of function phb3_pcicfg_filter_rc_pref_window(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Standardise on uint64_t pe_numberRussell Currey2016-08-301-47/+47
| | | | | | | | | | | | | | | Throughout skiboot (and the kernel) PE numbers are named "pe_no", "pe_num" and "pe_number", and sized as 16, 32 and 64bit uints depending on where you look. This is annoying and potentially misleading in cases such as the OPAL API, where different calls have different int sizes even though the PE number they want is the same. Fix this by making *everything* uint64_t pe_number. In doing this, there are some whitespace fixes and mve_number gets dragged into this as well for cases like set_msi_{32/64} where they essentially mean the same thing. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Update capi initialization sequenceFrederic Barrat2016-08-241-1/+2
| | | | | | | | | | | | | | The capi initialization sequence was revised in a circumvention document when a 'link down' error was converted from fatal to Endpoint Recoverable. Other, non-capi, register setup was corrected even before the initial open-source release of skiboot, but a few capi-related registers were not updated then, so this patch fixes it. The point is that a link-down error detected by the UTL logic will lead to an AIB fence, so that the CAPP unit can detect the error. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* interrupts: Add new source ->attributes callbackBenjamin Herrenschmidt2016-08-111-11/+15
| | | | | | | | | | | | | | This allows a given source to provide per-interrupt attributes such as whether it targets OPAL or Linux and it's estimated frequency. The former allows to get rid of the double set of ops used to decide which interrupts go where on some modules like the PHBs and the latter will be eventually used to implement smart caching of the source lookups. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb3: Increase AIB TX command credit for DMA read in CAPP DMA modeAndrew Donnellan2016-07-251-2/+11
| | | | | | | | | | | | | | When enabling CAPI in DMA mode, set the AIB TX command credits for channel 2 (DMA read) to 28, rather than 1. This significantly improves DMA read performance in CAPI DMA mode. Fixes: 5477148a439f ("phb3: Add support for CAPP DMA mode") Reported-by: John Walthour <jwalthour@us.ibm.com> Reported-by: Ricardo Mata <ricmata@us.ibm.com> Reported-by: Michael Perez <perezma@us.ibm.com> Cc: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* interrupts: Expose irq_source and change prototypes of all opsBenjamin Herrenschmidt2016-07-131-22/+15
| | | | | | | | | | | | This makes irq_source public, and change all irq_source_ops to take the source pointer as a first argument (they can still dig the void * data out of that). This will allow us to embed/wrap it for XIVE later on. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* interrupts: Use a #interrupt-cells of 2 for XICS interruptsBenjamin Herrenschmidt2016-07-121-1/+5
| | | | | | | | This is more compliant with PAPR, it will also allow us to use the second cell for other attributes on P9. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: fix inconsistent indentingStewart Smith2016-07-111-2/+2
| | | | | | | | Found by smatch static analysis (http://smatch.sourceforge.net/): hw/phb3.c:2331 capp_load_ucode() warn: inconsistent indenting hw/phb3.c:3444 phb3_set_capi_mode() warn: inconsistent indenting Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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