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* asm/head: balance branches to avoid link stack predictor mispredictsNicholas Piggin2019-04-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | The Linux wrapper for OPAL call and return is arranged like this: __opal_call: mflr r0 std r0,PPC_STK_LROFF(r1) LOAD_REG_ADDR(r11, opal_return) mtlr r11 hrfid -> OPAL opal_return: ld r0,PPC_STK_LROFF(r1) mtlr r0 blr When skiboot returns to Linux, it branches to LR (i.e., opal_return) with a blr. This unbalances the link stack predictor and will cause mispredicts back up the return stack. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head.S: set POWER9 radix HID bit at entryNicholas Piggin2019-04-171-0/+3
| | | | | | | | | | | When running in virtual memory mode, the radix MMU hid bit should not be changed, so set this in the initial boot SPR setup. As a side effect, fast reboot also has HID0:RADIX bit set by the shared spr init, so no need for an explicit call. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: move unnecessary code out of headNicholas Piggin2019-03-052-134/+139
| | | | | | | | | | | | | head.S should be for things that must be located in low memory, like boot and interrupt entry. Move some code from there into misc.S that is not called from entry routines. The motivation for this patch is work to run skiboot in virtual memory mode, which does not map head.S code. Even without that motivation, it's still good to keep head.S clean. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: implement support for MCE interrupts in powersaveNicholas Piggin2019-02-131-10/+37
| | | | | | | | | | | | | | The ISA specifies that MCE interrupts in power saving modes will enter at 0x200 with powersave bits in SRR1 set. This is not currently supported properly, the MCE will just happen like a normal interrupt, but GPRs could be lost, which would lead to crashes (e.g., r1, r2, r13 etc). So check the power save bits similarly to the sreset vector, and handle this properly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: allow recoverable sreset exceptionsNicholas Piggin2019-02-131-0/+4
| | | | | | | | This requires implementing the MSR[RI] bit. Then just allow all non-fatal sreset exceptions to recover. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: implement an exception handler for non-powersave sresetsNicholas Piggin2019-02-131-1/+19
| | | | | | | | Detect non-powersave sresets and send them to the normal exception handler which prints registers and stack. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: sreset handler remove FIXUP_ENDIANNicholas Piggin2019-02-131-15/+0
| | | | | | | | | | | | Remove FIXUP_ENDIAN from the normal sreset handler (not the fast reboot handler), to prevent it from trashing registers and CFAR. This mean sreset can be used to report a reliable register dump, and even be recoverable. A watchdog could be implemented to catch and diagnose stuck CPUs during boot using sreset. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/fast-reboot: fast reboot specific sreset patchNicholas Piggin2019-02-131-12/+25
| | | | | | | | | | | | Provide an sreset handler specifically for fast reboots, which allows FIXUP_ENDIAN to be removed from the normal sreset handler in the next patch. The save_1 == 0 condition is no longer required to signal a fast reboot. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: provide asm support for interrupts to be returned fromNicholas Piggin2019-02-132-18/+77
| | | | | | | | | | | | | | This adds the redzone to the interrupt stack, and code to restore registers. This can be used for a number of things. Initially it will be used to recover from system reset interrupts, it could later be used to handle recoverable machine checks, use the decrementer to implement a watchdog, handle HMI interrupts at boot, and to implement virtual memory. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: use HSRR exception registers in FIXUP_ENDIANNicholas Piggin2019-02-121-11/+12
| | | | | | | | | | | | | Taken from the Linux FIXUP_ENDIAN_HV macro, use the HSRR registers in FIXUP_ENDIAN. This allows the 0x100 exception handler (the single user of the macro) to preserve SRR registers and potentially recover, debug, or do something useful with them. This also allows the maco to be used in code with MSR[RI]=1, if the need arises. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: save current MSR in exception frameNicholas Piggin2019-02-122-0/+3
| | | | | | | | | Save and print the MSR of the interrupt context. This can be derived from the interrupt type, SRR1, and other system register settings. But it can be useful to quickly verify what's happening. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Add PVR_TYPE_P9PReza Arbab2019-02-102-2/+11
| | | | | | | Enable a new PVR to get us running on another p9 variant. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm: Fix up assembly for clangJoel Stanley2018-05-041-2/+2
| | | | | | | | | | | | asm/head.S:766:17: error: unknown operand or %r0,%r4,%r5, ^ asm/head.S:800:17: error: unknown operand or %r0,%r4,%r5, ^ Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: Fix comparison in opal_entry for switching to emergencyVaibhav Jain2018-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3fdd2629516d ("core/opal: Emergency stack for re-entry") introduced an emergency stack for re-entrant OPAL calls. A branch was added in opal_entry() that switches to emergency stack checks if current thread is already in an active opal call. However the conditional branch that checks the value cpu_thread->in_opal_call is reverse forcing the use of emergency stack in even in non re-entrant cases. This causes a opal stack guard routine __mcount_stack_check() to falsely assume that stack is overflown as stack pointer of EMERGENCY_STACK is compared against the bounds of NORMAL_STACK, forcing the function to call abort() with an error message of this form: INIT: Starting kernel at 0x20010000, fdt at 0x3073f708 53664 bytes) CPU 0004 Stack overflow detected ! pc=3001d8ec sp=31c27c90 (gap=30488) token=70 Aborting! CPU 0004 Backtrace: S: 0000000031c27b20 R: 000000003001ca2c E ._abort+0x60 S: 0000000031c27bb0 R: 0000000030013e10 E .__mcount_stack_check+0x168 S: 0000000031c27c90 R: 000000003001d8ec E .opal_entry_check+0x1c S: 0000000031c27d20 R: 00000000300051a4 E opal_entry+0xf4 --- OPAL call token: 0x46 caller R1: 0xc0000000011e3e50 --- So this patch update the 'bne' branch in opal_entry() to 'bgt' branch so that switch to emergency stack only happens when current cpu_thread->is_opal_call is greater than 1 indicating an re-entrant opal call. Fixes: 3fdd2629516d ("core/opal: Emergency stack for re-entry") Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Mahesh J Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/opal: Emergency stack for re-entryNicholas Piggin2018-04-181-4/+18
| | | | | | | | | | | | | | | | | | | | This detects OPAL being re-entered by the OS, and switches to an emergency stack if it was. This protects the firmware's main stack from re-entrancy and allows the OS to use NMI facilities for crash / debug functionality. Further nested re-entry will destroy the previous emergency stack and prevent returning, but those should be rare cases. This stack is sized at 16kB, which doubles the size of CPU stacks, so as not to introduce a regression in primary stack size. The 16kB stack originally had a 4kB machine check stack at the top, which was removed by 80eee1946 ("opal: Remove machine check interrupt patching in OPAL."). So it is possible the size could be tightened again, but that would require further analysis. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: implement quiescing without stack or clobbering regsNicholas Piggin2018-04-182-6/+68
| | | | | | | | | | | | | | | | | | | | | | | | Quiescing currently is implmeented in C in opal_entry before the opal call handler is called. This works well enough for simple cases like fast reset when one CPU wants all others out of the way. Linux would like to use it to prevent an sreset IPI from interrupting firmware, which could lead to deadlocks when crash dumping or entering the debugger. Linux interrupts do not recover well when returning back to general OPAL code, due to r13 not being restored. OPAL also can't be re-entered, which may happen e.g., from the debugger. So move the quiesce hold/reject to entry code, beore the stack or r1 or r13 registers are switched. OPAL can be interrupted and returned to or re-entered during this period. This does not completely solve all such problems. OPAL will be interrupted with sreset if the quiesce times out, and it can be interrupted by MCEs as well. These still have the issues above. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/stack: backtrace unwind basic OPAL call detailsNicholas Piggin2018-04-181-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put OPAL callers' r1 into the stack back chain, and then use that to unwind back to the OPAL entry frame (as opposed to boot entry, which has a 0 back chain). >From there, dump the OPAL call token and the caller's r1. A backtrace looks like this: CPU 0000 Backtrace: S: 0000000031c03ba0 R: 000000003001a548 ._abort+0x4c S: 0000000031c03c20 R: 000000003001baac .opal_run_pollers+0x3c S: 0000000031c03ca0 R: 000000003001bcbc .opal_poll_events+0xc4 S: 0000000031c03d20 R: 00000000300051dc opal_entry+0x12c --- OPAL call entry token: 0xa caller R1: 0xc0000000006d3b90 --- This is pretty basic for the moment, but it does give you the bottom of the Linux stack. It will allow some interesting improvements in future. First, with the eframe, all the call's parameters can be printed out as well. The ___backtrace / ___print_backtrace API needs to be reworked in order to support this, but it's otherwise very simple (see opal_trace_entry()). Second, it will allow Linux's stack to be passed back to Linux via a debugging opal call. This will allow Linux's BUG() or xmon to also print the Linux back trace in case of a NMI or MCE or watchdog lockup that hits in OPAL. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* mem-map: Use a symbolic constant for exception vector sizeNicholas Piggin2018-03-271-1/+1
| | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* build: use thin archives rather than incremental linkingNicholas Piggin2018-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | This changes to build system to use thin archives rather than incremental linking for built-in.o, similar to recent change to Linux. built-in.o is renamed to built-in.a, and is created as a thin archive with no index, for speed and size. All built-in.a are aggregated into a skiboot.tmp.a which is a thin archive built with an index, making it suitable or linking. This is input into the final link. The advantags of build size and linker code placement flexibility are not as great with skiboot as a bigger project like Linux, but it's a conceptually better way to build, and is more compatible with link time optimisation in toolchains which might be interesting for skiboot particularly for size reductions. Size of build tree before this patch is 34.4MB, afterwards 23.1MB. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/exception: beautify exception handler, add MCE-involved registersNicholas Piggin2018-02-082-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print DSISR and DAR, to help with deciphering machine check exceptions, and improve the output a bit, decode NIP symbol, improve alignment, etc. Also print a specific header for machine check, because we do expect to see these if there is a hardware failure. Before: [ 0.005968779,3] *********************************************** [ 0.005974102,3] Unexpected exception 200 ! [ 0.005978696,3] SRR0 : 000000003002ad80 SRR1 : 9000000000001000 [ 0.005985239,3] HSRR0: 00000000300027b4 HSRR1: 9000000030001000 [ 0.005991782,3] LR : 000000003002ad80 CTR : 0000000000000000 [ 0.005998130,3] CFAR : 00000000300b58bc [ 0.006002769,3] CR : 40000004 XER: 20000000 [ 0.006008069,3] GPR00: 000000003002ad80 GPR16: 0000000000000000 [ 0.006015170,3] GPR01: 0000000031c03bd0 GPR17: 0000000000000000 [...] After: [ 0.003287941,3] *********************************************** [ 0.003561769,3] Fatal MCE at 000000003002ad80 .nvram_init+0x24 [ 0.003579628,3] CFAR : 00000000300b5964 [ 0.003584268,3] SRR0 : 000000003002ad80 SRR1 : 9000000000001000 [ 0.003590812,3] HSRR0: 00000000300027b4 HSRR1: 9000000030001000 [ 0.003597355,3] DSISR: 00000000 DAR : 0000000000000000 [ 0.003603480,3] LR : 000000003002ad68 CTR : 0000000030093d80 [ 0.003609930,3] CR : 40000004 XER : 20000000 [ 0.003615698,3] GPR00: 00000000300149e8 GPR16: 0000000000000000 [ 0.003622799,3] GPR01: 0000000031c03bc0 GPR17: 0000000000000000 [...] Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/init: manage MSR[ME] explicitly, always enableNicholas Piggin2018-02-081-0/+29
| | | | | | | | | | | | | | | The current boot sequence inherits MSR[ME] from the IPL firmware, and never changes it. Some environments disable MSR[ME] (e.g., mambo), and others can enable it (hostboot). This has two problems. First, MSR[ME] must be disabled while in the process of taking over the interrupt vector from the previous environment. Second, after installing our machine check handler, MSR[ME] should be enabled to get some useful output rather than a checkstop. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add support for new gcc 7 parametrized stack protectorBenjamin Herrenschmidt2017-12-201-0/+5
| | | | | | | | This gives us per-cpu guard values as well. For now I just xor a magic constant with the CPU PIR value. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libstb/trustedboot.c: import tb_measure() from stb.cClaudio Carvalho2017-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This imports tb_measure() from stb.c, but now it calls the CVC sha512 wrapper to calculate the sha512 hash of the firmware image provided. In trustedboot.c, the tb_measure() is renamed to trustedboot_measure(). The new function, trustedboot_measure(), no longer checks if the container payload hash calculated at boot time matches with the hash found in the container header. A few reasons: - If the system admin wants the container header to be checked/validated, the secure boot jumper must be set. Otherwise, the container header information may not be reliable. - The container layout is expected to change over time. Skiboot would need to maintain a parser for each container layout change. - Skiboot could be checking the hash against a container version that is not supported by the Container-Verification-Code (CVC). The tb_measure() calls are updated to trustedboot_measure() in a subsequent patch. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* libstb/secureboot.c: import sb_verify() from stb.cClaudio Carvalho2017-12-182-3/+3
| | | | | | | | | | | | | This imports the sb_verify() function from stb.c, but now it calls the CVC verify wrapper in order to verify signed firmware images. The hw-key-hash and hw-key-hash-size initialized in secureboot.c are passed to the CVC verify function wrapper. In secureboot.c, the sb_verify() is renamed to secureboot_verify(). The sb_verify() calls are updated in a subsequent patch. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fast-reboot: quiesce opal before initiating a fast rebootNicholas Piggin2017-12-031-10/+0
| | | | | | | | | | | | | | | | | | | Switch fast reboot to use quiescing rather than "wait for a while". If firmware can not be quiesced, then fast reboot is skipped. This significantly improves the robustness of fast reboot in the face of bugs or unexpected latencies. Complexity of synchronization in fast-reboot is reduced, because we are guaranteed to be single-threaded when quiesce succeeds, so locks can be removed. In the case that firmware can be quiesced, then it will generally reduce fast reboot times by nearly 200ms, because quiescing usually takes very little time. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm/head: move opal entry token check into CNicholas Piggin2017-12-031-11/+2
| | | | | | | Move opal_check_token from asm to C. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm/head: add entry/exit callsNicholas Piggin2017-12-031-6/+10
| | | | | | | | | Add entry and exit C functions that can do some more complex checks before the opal proper call. This requires saving off volatile registers that have arguments in them. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/lock: Introduce atomic cmpxchg and implement try_lock with itNicholas Piggin2017-12-032-44/+1
| | | | | | | | | cmpxchg will be used in a subsequent change, and this reduces the amount of asm code. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart: fix some ifdef __TEST__ foo to ensure unittests work] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm/head: Loop after attnOliver O'Halloran2017-11-091-0/+1
| | | | | | | | | | We use the attn instruction to raise an error in early boot if OPAL don't recognise the PVR. It's possible for hostboot to disable the attn instruction before entering OPAL so add an extra busy loop after the attn to prevent attempting to boot on an unknown processor. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm/head: initialize preferred DSCR valueNicholas Piggin2017-10-291-3/+19
| | | | | | | POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle POWER9 power management implementationNicholas Piggin2017-09-281-21/+49
| | | | | | | | | | | | Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Set POWER9 RPR SPRMichael Neuling2017-06-301-0/+3
| | | | | | | | | Set POWER9 RPR SPR to 0x00000103070F1F3F. Same value as P8. Without this, thread priorities inside a core don't work. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add "cleanup_global_tlb" for P9 and laterBenjamin Herrenschmidt2017-06-261-0/+60
| | | | | | | | | | | | | Uses broadcast TLBIE's to cleanup the TLB on all cores and on the nest MMU By default this works with older binutils but there is a version (in #defines) that requires newer binutils and which documents what the instructions are. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Rename cleanup_tlb() to cleanup_local_tlb()Benjamin Herrenschmidt2017-06-261-2/+2
| | | | | | | | It uses tlbiel and only cleans up the TLB of the calling core Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Move cleanup_tlb from head.S to misc.SBenjamin Herrenschmidt2017-06-262-13/+13
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Update default TSCR for P9Michael Neuling2017-06-211-0/+3
| | | | | | | Update default TSCR value for P9 as recommended by HW folk. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Introduce smt_lowest()Nicholas Piggin2017-06-061-3/+3
| | | | | | | | | | | | Recent CPUs have introduced a lower SMT priority. This uses the Linux pattern of executing priority nops in descending order to get a simple portable way to put the CPU into lowest SMT priority. Introduce smt_lowest() and use it in place of smt_very_low and smt_low ; smt_very_low sequences. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* head.S: store LR rather than CTR when trying to store LRStewart Smith2017-05-081-1/+1
| | | | | | | | Long existing typo of r5 rather than r6, meaning we were storing CTR instead of LR. Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* head.S: store all of LR and CTROliver O'Halloran2017-05-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | When saving the CTR and LR registers the skiboot exception handlers use the 'stw' instruction which only saves the lower 32 bits of the register. Given these are both 64 bit registers this leads to some strange register dumps, for example: *********************************************** Unexpected exception 200 ! SRR0 : 0000000030016968 SRR1 : 9000000000201000 HSRR0: 0000000000000180 HSRR1: 9000000000001000 LR : 3003438830823f50 CTR : 3003438800000018 CFAR : 00000000300168fc CR : 40004208 XER: 00000000 In this dump the upper 32 bits of LR and CTR are actually stack gunk which obscures the underlying issue. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm: do not set SDR1 on POWER9Nicholas Piggin2017-04-071-1/+3
| | | | | | | This register does not exist in ISAv3. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm: Add POWER9 case to init_shared_sprsBenjamin Herrenschmidt2017-03-091-0/+24
| | | | | | | | For now, setup the HID and HMEER. We'll add more as we get good default values from HW. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm: Don't try to set LPCR:LPES1 on P8 and P9Benjamin Herrenschmidt2017-03-091-2/+28
| | | | | | | The bit doesn't exist Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* asm: Fix setting of LPCR:DPFDBenjamin Herrenschmidt2017-03-091-8/+2
| | | | | | | | | | | | | | We have code to set DPFD to 4 in init_shared_sprs, from the original commit, based on recommendations from HW. However, we immediately override this in init_replicated_sprs with the value 7. So let's remove the former and update the latter to set the value to 4. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Initial support for the ELFv2 ABINicholas Piggin2017-02-061-0/+1
| | | | | | | | | | | | Provide an experimental option to compile using ELFv2 ABI even on big endian builds. ELFv2 + BE is not officially supported by the toolchain, but it works quite well. It may be useful as a small step toward a little-endian build. This saves about 200kB of text/data. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* head: add new OPAL entry points to the NACAOliver O'Halloran2017-01-161-1/+4
| | | | | | | | The NACA now incorporates the entry points for the primary and secondary threads. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Stop using 3-operand cmp[l][i] for latest binutilsAlexey Kardashevskiy2016-12-201-2/+2
| | | | | | | | | | | Since a5721ba270, binutils does not support 3-operand cmp[l][i]. This adds (previously optional) parameter L. Hre is the binutils commit: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=a5721ba270ddf860e0e5a45bba456214e8eac2be;hp=b82317dd347991288e4cca4772e951c672fca8cc Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Convert RTC read from asm to CMichael Neuling2016-11-021-8/+0
| | | | | | | | Also moves some code around to ensure things are defined before they are used. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Convert console read/write from asm to CMichael Neuling2016-11-021-18/+0
| | | | | | | | Also changes the function name: mambo_read/write() -> mambo_console_read/write() Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* mambo: Convert sim exit from asm to CMichael Neuling2016-11-021-6/+0
| | | | | Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fast reboot for P8Benjamin Herrenschmidt2016-10-171-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an experimental patch that implements "Fast reboot" on P8 machines. The basic idea is that when the OS calls OPAL reboot, we gather all the threads in the system using a combination of patching the reset vector and soft-resetting them, then cleanup a few bits of hardware (we do re-probe PCIe for example), and reload & restart the bootloader. For Trusted Boot, this means we *add* measurements to the TPM, so you will get *different* PCR values as compared to a full IPL. This makes sense as if you want to be sure you are running something known then, well, do a full IPL as soft reset should never be trusted to clear any malicious code. This is very experimental and needs a lot of testing and also auditing code for other bits of HW that might need to be cleaned up. BenH TODO: I also need to check if we are properly PERST'ing PCI devices. This is partially based on old code I had to do that on P7. I only support it on P8 though as there are issues with the PSI interrupts on P7 that cannot be reliably solved. Even though this should be considered somewhat experimental, we've had a lot of success on a variety of machines. Dozens/hundreds of reboots across Tuleta, Garrison and Habanero. Currently, we've hidden it behind a NVRAM config option, which *is* liable to change in the future (to ensure that only those who know what they're doing enable it) You can enable the experimental support via nvram option: nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes from Mikey] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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