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* Updated gerrit hostnameSumit Kumar2018-07-201-2/+2
| | | | | | | Change-Id: Ie55fd178758591fbed96187c94c2cc1b00eac024 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62924 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.pci.scan.initfile -- replace 62028 implementation with initfile entryJoe McGill2018-07-192-111/+0
| | | | | | | | | | | | | | | | | | | | | | 62028 added a workaround for SW 430383, using a manual re-scan of the ring hardcoded to flip the desired bits because engineering data was not yet available for the necessary spies This commit removes the SBE manual scan sequence and sets the necessary chicken switches by the newly added spy entries Change-Id: I912f190ab44c320f9bd142ce626570d34ec0b00f CQ: SW438480 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62675 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62710 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: remove chiplet enable drop in core_poweron for multicast scomYue Du2018-07-181-4/+1
| | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I388c81cc1af356231daa4a11702a3a84dcc222c9 CQ: SW437797 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62302 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62326 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabledJoe McGill2018-07-183-0/+30
| | | | | | | | | | | | | | | Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Avoid spurious Malf Alert (HMI) to PHYP in PM Complex Reset/SuspendAmit Tendolkar2018-07-131-0/+7
| | | | | | | | | | | | | | | | | | | Reseting the engines potentially causes another to send the PM Malf Alert to PHYP. Disable in PM Reset and let SGPE re-enable in PM Init. Added a similar safe check and disable in MPIPL path for pm_suspend Change-Id: If9fd572d156a8f280b0fd204175e5ccf0969b249 CQ: SW436905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62135 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62298 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Clockgate disable workaround for HW452921Nick Klazynski2018-07-131-3/+3
| | | | | | | | | | | | | | | Change-Id: I09ec35894a488f0c9e2b03d8726b3a5a3ce08fcf CQ: HW452921 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62048 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62067 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cleanup: Updated Mvpd access function and removal of unused ringsClaus Michael Olsen2018-07-133-18/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Removed the function that converts the outdated RS4v2 header format to the current RS4v3 header format in the Mvpd accessor functions, mvpdRingFundFind(). This can be done since all Mvpd in existance on any of our supported P9 systems (i.e., >=P9N DD20) use RS4v3. - Removed two #R rings which are no longer supported since P9n DD10. Because these rings happen to be located at the end of the TOR instance ring sections, it will alter the image, but will not interfere with the traversing of the ringSection image due to the way chiplet and common/instance sub-sections are partitioned. Key_Cronus_Test=XIP_REGRESS Change-Id: I39740a099b224bfade8a97a057453b85498e5880 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61100 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Michael C. Sgro <mcs793@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61288 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Marking CME sram addr and cntrl register for whitelistPrasad Bg Ranganath2018-07-131-0/+4
| | | | | | | | | | | | Change-Id: I480a7bb511718cbd2e04a2ca5b41585ce9ce1606 CQ:SW437569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61879 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61881
* Secure memory allocation and setupJenny Huynh2018-07-129-16/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Inverted logic of hasClock bit in Clock Status registerRaja Das2018-07-121-0/+4
| | | | | | | | | | | | | CQ: SW437571 Change-Id: I9101adc63225a97aeddf445519fa660d961c3d9c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61463 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61471 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix in quisceSachin Gupta2018-07-122-8/+6
| | | | | | | | | | | | Change-Id: Id64bf0b948e65b142e47b777f937ffe4bf530d55 CQ: SW437514 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62208 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit c2da12c625e492988947fdb872424f10d0b8b4b1) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62293
* Suspend async task on quiesce SBEspashabk-in2018-07-121-19/+30
| | | | | | | | | | Change-Id: Icfe25bdd137c1f30a8a1c210fa6d935612d61e68 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 98d57c57fdd8ca52b4f7a71345ba5d4322a3aff9) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62204
* Skip select master EX on slave SBEspashabk-in2018-07-121-7/+10
| | | | | | | | | | | CQ: SW432854 Change-Id: I5bd4f32e77fe8abb7193f5bcff6f298c75b65b8c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62015 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit ccafed91129314fb72a13321c4826f64685f2fa7) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62117
* p9_sbe_check_quiesce -- restore call to p9_int_scrub_cachesJoe McGill2018-07-123-3/+53
| | | | | | | | | | | | | | | | | | | | | | 52512 removed code related to the DD1 SW based INT reset sequence, to leave only the HW based reset in production code for DD2 and beyond. It also erroneously removed the call to/code for p9_int_scrub_caches. This commit restores the subroutine, and invokes it prior to the HW quiesce/sync reset into order to scrub/flush the EQC, VPC, IVC, and SBC caches. Change-Id: I051117e3a18c55aea7267e53eea1652f0cff9790 CQ: SW431898 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62227 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62243 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* set PEC disable store thread based ordering chicken switchesJoe McGill2018-07-103-1/+141
| | | | | | | | | | | | | | | | Change-Id: I2d9aed7833a1bf43c797689d50ff32794ef54cff CQ: SW430383 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62028 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62042 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* allow option to enforce mirroring of all system memoryJoe McGill2018-07-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nest_attributes.xml: add REQUESTED enum to ATTR_MRW_HW_MIRRORING_ENABLE, takes prior behavior of TRUE enum new TRUE enum behavior enforces that all memory will be mirrored p9_mss_eff_grouping: prohibit group formation of size 1, 2 (cross-MCS), or 3 if ATTR_MRW_HW_MIRRORING_ENABLE is TRUE -- this will ensure that all groups formed support mirroring commit log for each DIMM which is ungrouped p9_mss_setup_bars, p9_query_mssinfo, p9_setup_bars: Minor changes to adapt to new enum definition Change-Id: I328b7b063bf79d534b1b466560309c0ccae5a4f5 CQ: SW436871 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61483 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Ravi Medikonduru <ravimed1@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61496 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Set up oscillator error mask based on MF osc settingJoachim Fenkes2018-07-042-29/+32
| | | | | | | | | | | | | | | | | | | | | | | | On Cumulus, set up the oscerr mask (0102001A) such that errors on unused MF/PCI oscillators are masked (based on the setup in RC3), making sure the corresponding FIR bit (TP LFIR bit 37) will not report false positives. Keep the mask constant for Nimbus as only MF oscillator 0 is in use there. This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5 because a correct mask setting here obviates the need for selective FIR masking. Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Added support for enable disable of 24x7 IMA.Prem Shanker Jha2018-07-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | Commit incorporates an ability to enable or disable 24x7 IMA. It reads an attribute and populates a field of QPMR header. 24x7 firmware is expected to read this field and enable or disable 24x7 IMA by itself. Key_Cronus_Test=NO_TEST Change-Id: I1f1fc738a58f11346f7972eb3c547aac0e2f805f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59443 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59450 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Protect fapi rc between processor and async threadspashabk-in2018-07-032-2/+9
| | | | | | | | | | | | | | | Since we share a global fapi rc betweeen threads, to avoid corruption, following approach - 1. Run processor thread at higher priority than async thread 2. Once async thread is unlocked, make it non pre-emptable Change-Id: I873affbc15d99c8020c3d074e58aae1165e7ae12 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61355 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit bcd84270938b75c83cc364ff2c75133638cddb6e) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61461
* Alink Hot Repair FixChris Steffen2018-07-021-0/+18
| | | | | | | | | | | | | | | Change-Id: Ie6fc10cefe5084af41a14c5edfd31d4cdc6f591d CQ: HW446279 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61067 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gary A. Peterson <garyp@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61245 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_lpc_init: Add final check for errorsJoachim Fenkes2018-07-023-0/+38
| | | | | | | | | | | | | | | | | Add an external FFDC collection procedure that will dump the LPC register spaces, make sure it is called if after LPC setup an OPB error is registered. Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b CQ: SW435433 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60994 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Optimize PSU testcasesspashabk-in2018-06-293-45/+34
| | | | | | | | | | | | | 1. Remove unnecessary prints 2. Remove unnecessary run cycles Change-Id: I03fd82cc8232a4d187cce75c7b5745a47a21ea8b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61453 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 01f2f1c1b8a91c8abbcabb100647d4006fe4cecf) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61649
* ppe CI memory testcase failure fixspashabk-in2018-06-292-475/+181
| | | | | | | | | Change-Id: I855efb072539516c2490cdf63e480b46214db27c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61249 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61648
* Update memory address of ADU testcasespashabk-in2018-06-291-62/+64
| | | | | | | | | | Change-Id: Ibe9a7bde7e0471309792ac19b3e3aa0dd15e418f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61053 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 8487bc87a8908420b689b2f13688000240689154) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61646
* Check for system checkstop for individual mpipl stepspashabk-in2018-06-271-4/+7
| | | | | | | | | | Change-Id: I0633a40a1c1f1b69be3e0c0db071adb9a5b9c6df Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61456 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 88b93b1f8c7c1dedb851c50e914be90838f46a7e) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58618 Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating p9.core.scan.initfile settings for p9n 2.3Ben Gass2018-06-261-2/+16
| | | | | | | | | | | | | | | | | | HW407187 workaround should not be applied to p9n 2.3 HW407165 workaround should be applied to p9n 2.3 using new spy HW431323 should be applied to p9n 2.3 Change-Id: I458df430d89dee66342e62afab704abe321b8d6e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60494 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60500 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add more fapi2 target types for AxoneMatt K. Light2018-06-263-9/+28
| | | | | | | | | | | | | | | Change-Id: Ie825c3e9034f657aed821c43ebafb242bd125cd5 Signed-off-by: Matt K. Light <mklight@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57946 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57956 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Increase PB Purge time for MPIPL to accommodate FleetwoodGreg Still2018-06-261-2/+2
| | | | | | | | | | | | | | Change-Id: Ic7cab359607c84eeec32e2e95270706e8c0075f1 CQ: SW434802 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61193 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61204 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Don't meddle with osclite controls on CumulusJoachim Fenkes2018-06-261-11/+11
| | | | | | | | | | | | | | | | | | | | | | During the clock_test2 substep, the procedure would unconditionally clear use_osc_1_0 from ROOT_CTRL3, which turns the use_osc field (that has been set up in istep 0) into an invalid value and breaks redundant PCI clock failover. Not removing that piece of code altogether because it does not appear to hurt anything on Nimbus and it was explicitly requested by Uli back in the Nimbus days, even though we don't remember his rationale. Change-Id: Ieffe1946980a65c302f60d80f83b527e24d74b3b CQ: SW434930 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61188 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61230 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* remove whitespace and newlines from target before processingMatt K. Light2018-06-261-1/+6
| | | | | | | | | | | | Change-Id: Ib376268c58360b4cb5684603486397a492fb7f94 Signed-off-by: Matt K. Light <mklight@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61344 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit ffcc8708c85a0aa5348e9ef024f439d413ab739b) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61292 Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix timer issue in Async taskspashabk-in2018-06-261-2/+2
| | | | | | | | | | | Change-Id: I5a4c6b2a4f693497901bc93d446c6fd60bca5c85 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61275 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 6bba2c2286ededc42bca29b74b09e1d032f52a25) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61345
* Add RL0/RL1 support for CDD1.2Nick Klazynski2018-06-241-8/+31
| | | | | | | | | | | | | | Change-Id: I21d861481b9909ea024934e8b5830521d407c9a7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60873 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60884 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* remove whitespace and newlines from target before processingMatt K. Light2018-06-231-1/+5
| | | | | | | | | | Change-Id: Id3b17da6b9a0adc26da72aa3e3779721d9f26085 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61038 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit f8a3bdd8f4ffcbfbb791111dad9e7415bba23ceb) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58570
* Workaround for vector pool issueSachin Gupta2018-06-222-6/+13
| | | | | | | | | Change-Id: I2a158ecbd6125a46341456ec5699c9c87d242a14 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61167 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 82b4709602c4265d780518394ffed58ba74ccaa8) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61168
* Fill MBOX response on get capabilitiesspashabk-in2018-06-202-0/+26
| | | | | | | | Change-Id: I0d5f9cbc940a5f84278acea96d5f963b3a0a4d9e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59726 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Move some istep code to seepromSachin Gupta2018-06-201-13/+13
| | | | | | | | | | | Change-Id: I60dc9bc306b16920e677615914dfa045e2584698 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60951 Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit c01a3a6d51bfdd6773d6eca601a3b55ed5259b24) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60954
* Use Greylist in PutScomUnderMaskSachin Gupta2018-06-209-16/+42
| | | | | | | | | | | RTC: 195177 Change-Id: I1728d78b2019b5a3d5da24c18baf676d07b93de2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60765 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 33f754c5c94daa873ca40e0a8accd43f3087ec5d) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60943
* Support periodic timerspashabk-in2018-06-198-7/+69
| | | | | | | | | | | | | This timer will be sued to toggle EI bus after every 24 hours. Change-Id: Id21af317914ddfb02d42a166bc7c0b6ce62bffdd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60777 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 4fe7e7c6520087ec1416e332be2b0b8ca85574d4) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48096
* Support for greylistSachin Gupta2018-06-193-4/+100
| | | | | | | | | | | | | | | In this commit support is added to parse bit mask and create data structure in sbe. Change-Id: Ia7a532de138dbd879d2bf5d54ce5d315884d0469 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60761 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit a2139de912b1513f0a1f0c5967aa1e6b413961b2) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60675
* correctly propogate bad return code from p9_adu_coherent_status_checkJoe McGill2018-06-182-9/+17
| | | | | | | | | | | | | | | | | | | p9_adu_access.C p9_adu_setup.C save current_err to local return code object at start of exit path, and return the saved value at exit (prior code was clobbering current_err by call to cleanup routines) Change-Id: I2f247ba2e93c673b3581e3ebe1504d4f05cb3a24 CQ: SW434090 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60607 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60618 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support new field for greylistSachin Gupta2018-06-181-980/+980
| | | | | | | | | | | | | | | | New field Bit Mask has been added. If this field is present, only putScomUnderMask is allowed. Mask in putScomUnderMask should be either same or superset of Bit Mask in greylist. Change-Id: Ibc0ff61918f15ab0193e7cbe55080b7573d11f2e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60683 Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60689 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR 37 only when MF oscswitch redundancy enabledJoe McGill2018-06-182-3/+13
| | | | | | | | | | | | | | Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adapt p9_sbe_check_master_stop15 for bad path on non-SBE platforms for fleetwoodAmit Tendolkar2018-06-173-29/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. On PENDING/INVALID_STATE RCs, need some FFDC and service actions on FSP using regular FAPI mechanisms like FAPI_ASSERT and register ffdc colletion 2. SBE still uses existing mechanism and restrictions - optimized for space a. no fapi error xml based callbacks b. no fapi error xml based register ffdc collection c. max local ffdc members < 20 d. depends on p9_collect_deadman_ffdc for FFDC with RC TIMEOUT 3. Compile out extra code on SBE builds Change-Id: Id35f9a7dbfc7e423bd7cf0846f493a8270a48cd6 CQ: SW430391 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60320 Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60391 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* shift OBUS FIR programming inits for secure bootJoe McGill2018-06-172-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_scominit: unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE platform only) p9_fab_iovalid: conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14 (will handle unmasking here when insecure -- Cronus or old SBE images) p9_obus_extfir_setup: new HWP for HB to call, mask OBUS EXTFIR bits for unused busses Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361
* Add TOD delay register in whitelistSachin Gupta2018-06-141-0/+1
| | | | | | | | | | | | Change-Id: I19845b7376170935b3f5715e01c7f0381f4b4f60 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60543 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60547 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_security_white_black_list -- add whitelist entries for OBUS FBC link bringupJoe McGill2018-06-141-0/+20
| | | | | | | | | | | Change-Id: I751a3cf36abf355f5b53ab29a64b763a7ffaab2b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60238 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60249
* Update whitelist for p9_block_wakeup_intrSachin Gupta2018-06-141-0/+3
| | | | | | | | | | | | | Change-Id: I9dce4fd043a05cce88a08940ea7131f255c3eb99 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60373 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9n_23 engd with n23_e9108_3_tp105_ec408_soa_sc_u138_01 dataBen Gass2018-06-131-1/+15
| | | | | | | | | | | | | | Change-Id: Ib586128b6152c2afb300b984c115d0d9fa8e0e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59588 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59596 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SBE Tool support for fleetwood systemsRaja Das2018-06-124-76/+169
| | | | | | | | | Change-Id: Ic395ca1d1bde3aeabdacfefc473600d58585ff2b RTC:158861 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58691 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_common -- mark TP LFIR bit 37 as recoverableJoe McGill2018-06-111-1/+1
| | | | | | | | | | | | | | | | | | | TP LFIR 37 is meant to be marked recoverable for Cumulus 60118 unmasked the bit, but the default action register settings are programmed to trigger a checkstop. This adjust the action1 register default to recoverable. Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60261 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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