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authorJoachim Fenkes <fenkes@de.ibm.com>2018-02-21 09:31:25 +0100
committerSachin Gupta <sgupta2m@in.ibm.com>2018-07-02 06:15:33 -0400
commita8686c27d27e85e65fabea3af914e975ee8de509 (patch)
tree29e4b489e7cc894d99427a88227eb457506469c6 /src
parentc6fdb271fa1a9d1bebf6e78983c319eaf18d90b4 (diff)
downloadtalos-sbe-a8686c27d27e85e65fabea3af914e975ee8de509.tar.gz
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p9_sbe_lpc_init: Add final check for errors
Add an external FFDC collection procedure that will dump the LPC register spaces, make sure it is called if after LPC setup an OPB error is registered. Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b CQ: SW435433 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60994 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C11
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H2
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml25
3 files changed, 38 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
index 919b9e1d..02636eff 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
@@ -176,6 +176,17 @@ fapi2::ReturnCode p9_sbe_lpc_init(
FAPI_TRY(lpc_write(i_target_chip, LPCM_LPC_MASTER_TIMEOUT_REG, LPCM_LPC_MASTER_TIMEOUT_VALUE),
"Error trying to set up the LPC host controller timeout");
+ //------------------------------------------------------------------------------------------
+ //--- STEP 4: Check that everyone is happy
+ //------------------------------------------------------------------------------------------
+ FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_STATUS_REG, l_data32),
+ "Error reading OPB master status register");
+ FAPI_ASSERT(0 == (l_data32 & LPCM_OPB_MASTER_STATUS_ERROR_BITS),
+ fapi2::LPC_OPB_ERROR().
+ set_FFDC_TARGET_CHIP(i_target_chip).
+ set_TARGET_CHIP(i_target_chip),
+ "The OPB master indicated an error after LPC setup");
+
FAPI_DBG("p9_sbe_lpc_init: Exiting ...");
fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
index 75852847..91301726 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
@@ -54,6 +54,8 @@ extern "C"
const uint64_t LPC_LRESET_OE = 23;
const uint64_t LPC_LRESET_OUT = 22;
const uint32_t LPC_LRESET_DELAY_NS = 200000;
+ const uint32_t LPCM_OPB_MASTER_STATUS_REG = 0xC0010000;
+ const uint32_t LPCM_OPB_MASTER_STATUS_ERROR_BITS = 0x20000FC3;
const uint32_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008;
const uint32_t LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE = 2;
const uint32_t LPCM_OPB_MASTER_TIMEOUT_REG = 0xC0010040;
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
index 1668a29e..71c2bff8 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_lpc_init_errors.xml
@@ -45,4 +45,29 @@
<target>TARGET_CHIP</target>
</deconfigure>
</hwpError>
+ <hwpError>
+ <sbeError/>
+ <rc>RC_LPC_OPB_ERROR</rc>
+ <description>After LPC initialization, the OPB master indicated an error.</description>
+ <collectFfdc>p9_collect_lpc_regs, FFDC_TARGET_CHIP</collectFfdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <target>TARGET_CHIP</target>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <priority>MEDIUM</priority>
+ </callout>
+ <deconfigure>
+ <target>TARGET_CHIP</target>
+ </deconfigure>
+ </hwpError>
+ <hwpError>
+ <rc>RC_LPC_REGISTERS</rc>
+ <description>LPC register dump</description>
+ <buffer>OPB_MST_REGS</buffer>
+ <buffer>OPB_ARB_REGS</buffer>
+ <buffer>LPC_HC_REGS</buffer>
+ </hwpError>
</hwpErrors>
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