summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
Commit message (Expand)AuthorAgeFilesLines
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-151-0/+34
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-35/+1
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-19/+1
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-01-011-0/+18
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-201-0/+17
* Add Memory Subsystem FIR supportBrian Silver2016-12-201-0/+17
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2016-12-201-1/+72
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-201-1/+20
* scan inits for lab workaround for DI bug HW392781Shelton Leung2016-11-301-0/+17
* Adding workaround for HW930007 and HW386013Jenny Huynh2016-11-211-0/+18
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-211-0/+16
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-0/+18
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-101-12/+140
* p9_psi_init -- parametrize link speed (half/full)Joe McGill2016-10-311-0/+18
* PPM reg collision (HW389511) work-around: Special Wake-upChristopher Riedl2016-10-261-0/+17
* p9.fbc.scan.initfile -- create initfile, add workaround for HW376651Joe McGill2016-10-181-0/+18
* HW388878 VCS workaroundJoe McGill2016-10-121-3/+3
* Cache HWP: DD1 VCS WorkaroundYue Du2016-10-111-0/+18
* Change chip to unsecure always for DD1 chipsSoma BhanuTej2016-10-101-0/+18
* DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-10-101-19/+1
* Update file headersSachin Gupta2016-09-161-1/+1
* SBE move import`Shakeeb2016-09-011-0/+184
OpenPOWER on IntegriCloud