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authorYue Du <daviddu@us.ibm.com>2016-10-06 14:59:16 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2016-10-11 13:42:02 -0400
commit338653266e2a4b4bf2218616e210c825975c1889 (patch)
tree923eec7ca589b7c5fe1bd7a094e8a31ff09fb3ce /src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
parentabdcae23020a3926e67c43f992afacde948b9004 (diff)
downloadtalos-sbe-338653266e2a4b4bf2218616e210c825975c1889.tar.gz
talos-sbe-338653266e2a4b4bf2218616e210c825975c1889.zip
Cache HWP: DD1 VCS Workaround
Change-Id: I9634a767878904f810cb1e6a0767ba4bbad241cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30827 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30888 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml')
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 1520a140..88943072 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -181,4 +181,22 @@
</chip>
</chipEcFeature>
</attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ DD1 only: enable VCS workaround in istep4 cache hwp. This is used by
+ the procedure for p9_hcd_cache_poweron and p9_hcd_cache_chiplet_reset.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
</attributes>
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