| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Axone support to TP stopclocks | Soma BhanuTej | 2018-03-02 | 3 | -46/+104 |
| * | LPC: Add empty files for mirroring to HB, PPE, HWSV | Joachim Fenkes | 2018-02-22 | 1 | -0/+24 |
| * | Additional risk level support - (step 2) Updating the image w/RL2 | Claus Michael Olsen | 2018-02-17 | 1 | -14/+1 |
| * | Mask TP LFIR for non PPE mode - p9_sbe_common | Soma BhanuTej | 2018-02-15 | 1 | -1/+9 |
| * | Revert "p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock"" | Sachin Gupta | 2018-02-10 | 1 | -3/+64 |
| * | Make SBE errors recoverable - p9_sbe_common | Soma BhanuTej | 2018-01-26 | 1 | -3/+3 |
| * | p9_sbe_chiplet_reset: Remove SIM_ONLY conditional around delay | Joachim Fenkes | 2018-01-13 | 1 | -3/+1 |
| * | p9_sbe_tp_chiplet_init3: Honor PCI osc selection when checking for osc errors | Joachim Fenkes | 2018-01-12 | 1 | -8/+12 |
| * | support customized application of filter PLL buckets from AW MVPD keyword | Joe McGill | 2017-12-12 | 2 | -19/+72 |
| * | Revert "p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock" | Sachin Gupta | 2017-12-12 | 1 | -63/+2 |
| * | p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock | Joachim Fenkes | 2017-12-11 | 1 | -2/+63 |
| * | Enhance SBE Deadman FFDC Format and sequencing | Amit Tendolkar | 2017-12-11 | 1 | -15/+6 |
| * | Handle security security bit in p9_sbe_attr_setup | spashabk-in | 2017-12-04 | 1 | -20/+38 |
| * | remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstate | Joe McGill | 2017-11-28 | 2 | -41/+64 |
| * | PM: Fix QCSR and CCSR update | Prasad Bg Ranganath | 2017-11-13 | 1 | -6/+9 |
| * | Fix to skip Osc check in sim only | Soma BhanuTej | 2017-11-02 | 1 | -57/+76 |
| * | Make plat init attributes non-writable | Santosh Puranik | 2017-10-27 | 1 | -236/+7 |
| * | osclite status check in clock_test2 | Anusha Reddy Rangareddygari | 2017-10-26 | 1 | -10/+28 |
| * | Axone Update | Anusha Reddy Rangareddygari | 2017-10-24 | 1 | -28/+68 |
| * | Update hardware procedure metadata | Anusha Reddy Rangareddygari | 2017-10-24 | 1 | -1/+1 |
| * | p9_setup_clock_term updates | Anusha Reddy Rangareddygari | 2017-10-24 | 1 | -3/+5 |
| * | Cumulus proc updates | Anusha Reddy Rangareddygari | 2017-10-23 | 1 | -1/+4 |
| * | Level 2 HWP for p9_setup_clock_term | Anusha Reddy Rangareddygari | 2017-10-23 | 1 | -13/+36 |
| * | L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2 | Abhishek Agarwal | 2017-10-23 | 1 | -0/+62 |
| * | p9_sbe_chiplet_reset: Set VITL_AL flag for MC chiplets | Joachim Fenkes | 2017-10-09 | 2 | -0/+6 |
| * | p9_sbe_tp_enable_ridi -- restore old behavior for cache contained mode support | Joe McGill | 2017-10-06 | 1 | -1/+24 |
| * | Revert PLL unlock commits of 45102 and 46563 | Yue Du | 2017-10-05 | 1 | -7/+3 |
| * | {nest,cache}_pll_setup: Properly clear PLL unlock indication | Joachim Fenkes | 2017-10-04 | 1 | -3/+3 |
| * | Update hardware procedure metadata | Anusha Reddy Rangareddygari | 2017-10-04 | 70 | -103/+103 |
| * | Remove functionality from tp enable ridi and move it to nest enabled ridi | Christian Geddes | 2017-10-02 | 3 | -26/+47 |
| * | Allow request fused mode bit when in HW fused mode | Dean Sanner | 2017-09-22 | 1 | -2/+4 |
| * | ATTR_CHIP_EC_FEATURE_HW406337 support for Axone | Abhishek Agarwal | 2017-09-12 | 1 | -2/+2 |
| * | resolve Zeppelin DMI channel framelock issues | Joe McGill | 2017-09-12 | 2 | -1/+20 |
| * | Ensure SGPE is disabled and ensure writes are enabled during pm_suspend | crgeddes | 2017-08-31 | 1 | -9/+0 |
| * | p9_sbe_tracearray: Add chip type detection to support changed p9c MC traces | Joachim Fenkes | 2017-08-29 | 1 | -47/+88 |
| * | Move clearing of CPMMR PPM WRITE DISABLE so it called on all func cores | crgeddes | 2017-08-24 | 1 | -7/+9 |
| * | Optimise RamCore put_reg & get_reg | spashabk-in | 2017-08-23 | 1 | -261/+194 |
| * | Clear disable_ppm_writes bit on CPPM register prior to setting PFDLY | crgeddes | 2017-08-18 | 2 | -0/+8 |
| * | Synchronous stopclk procedure for Quad | Soma BhanuTej | 2017-08-16 | 2 | -22/+33 |
| * | p9_sbe_lpc_init: Fix LPC bus LRESET for DD2 | Joachim Fenkes | 2017-08-16 | 2 | -64/+111 |
| * | p9_sbe_common -- update TP LFIR to match RAS XML v95 | Joe McGill | 2017-08-10 | 1 | -1/+1 |
| * | L3 Update - p9_ram_core HWPs | Thi Tran | 2017-08-08 | 2 | -79/+100 |
| * | p9_sbe_chiplet_pll_initf: Level 3 | Joachim Fenkes | 2017-07-26 | 2 | -3/+3 |
| * | p9_sbe_npll_setup: Level 3 | Joachim Fenkes | 2017-07-26 | 2 | -4/+4 |
| * | p9_sbe_npll_initf: Level 3 | Joachim Fenkes | 2017-07-26 | 2 | -3/+3 |
| * | p9_hcd_cache_dcc_skewadjust_setup.C | Anusha Reddy Rangareddygari | 2017-07-26 | 1 | -2/+2 |
| * | TP, Nest FIR updates -- DD2 updates to match RAS XML | Joe McGill | 2017-07-26 | 2 | -9/+21 |
| * | p9_sbe_tp_chiplet_init3: Level 3 | Joachim Fenkes | 2017-07-25 | 2 | -3/+3 |
| * | p9_sbe_tracearray: Nimbus DD2 updates | Joachim Fenkes | 2017-07-24 | 1 | -59/+132 |
| * | p9_sbe_check_master_stop15: Level 3 | Joachim Fenkes | 2017-07-20 | 2 | -9/+15 |
