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path: root/src/import/chips/p9/procedures/hwp/perv
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* FIR updates -- pervasive/core/PPEJoe McGill2017-02-021-46/+46
* Adding in LPC and OPB timeout valuesCHRISTINA L. GRAVES2017-02-011-2/+16
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-312-24/+108
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-241-68/+27
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-241-3/+13
* p9_sbe_attr_setup optimizedAnusha Reddy Rangareddygari2017-01-241-35/+13
* p9_sbe_tp_chiplet_init1 optimizedAnusha Reddy Rangareddygari2017-01-241-26/+22
* istep 4: only use one EX even if both are goodGreg Still2017-01-191-3/+25
* p9_sbe_startclock_chiplets optimizedAnusha Reddy Rangareddygari2017-01-181-146/+45
* p9_sbe_chiplet_pll_setup optimizedAnusha Reddy Rangareddygari2017-01-181-162/+111
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-5/+27
* Modify signature of p9_stopclocksspashabk-in2017-01-162-70/+99
* p9_stopclocks SBE/PPE related changesspashabk-in2017-01-164-31/+205
* Implementation of PIB stopclock with CBSSoma BhanuTej2017-01-164-51/+231
* Adding bool for cache/cores in the p9_stopclocks HWPSoma BhanuTej2017-01-162-9/+25
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2017-01-161-3/+3
* Stopclock procedure updatesSoma BhanuTej2017-01-164-56/+110
* Fixing a bug in stopclk cmn module - p9_common_stopclocksSoma BhanuTej2017-01-162-3/+3
* Fapi Implementation of Level2 HWP p9_stopclocksSoma BhanuTej2017-01-1610-19/+1060
* Level 1 HWP for p9_stopclocksSoma BhanuTej2017-01-162-0/+150
* configure FBC pump mode in SBEJoe McGill2017-01-151-1/+32
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-01-042-18/+27
* update core internal/external hang timeoutsJoe McGill2016-12-201-1/+1
* p9_sbe_nest_startclocks.C optimizedRaja Das2016-12-201-229/+95
* p9_sbe_chiplet_reset.C optimizedRaja Das2016-12-201-540/+476
* Update p9_clkoff_getreg/p9_ram_core proceduresLiuYangFan2016-11-301-3/+6
* Change auto variables to referencesspashabk-in2016-11-2215-82/+82
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-211-0/+32
* p9_sbe_attr_setup updatesAnusha Reddy Rangareddygari2016-11-211-0/+6
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-0/+4
* Add get XFVC in p9_clkoff_getreg and fix some issues in ramming procedureLiuYangFan2016-11-101-14/+131
* Move to additive multicast group setup for cores and caches in single modeGreg Still2016-11-092-79/+145
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-082-0/+116
* Commit for PLL unlock error unmask in pcb slave config reg IPL xls Ver 222Srinivas Naga2016-11-082-0/+23
* p9_sbe_tp_chiplet_init1: Enable PCB automatic reset on timeoutJoachim Fenkes2016-11-041-0/+4
* Fix for premature SBE<>HB STOP 15 deadman exitGreg Still2016-11-041-1/+1
* p9_sbe_attr_setupAnusha Reddy Rangareddygari2016-11-041-13/+272
* Fix ramming procedure issueLiuYangFan2016-11-011-2/+2
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-10-281-1/+79
* Fixing order of setting clock muxes & functional reset & removing sim only scomsCHRISTINA L. GRAVES2016-10-271-40/+5
* p9_sbe_chiplet_reset -- correct swapped FBC early/early exit hang poll timersJoe McGill2016-10-251-4/+4
* p9_sbe_scominit update for Async MCAbhishek Agarwal2016-10-212-0/+136
* Change clock mux setting to targets PRESENTAnusha Reddy Rangareddygari2016-10-211-4/+4
* Cleaned old makefilesSachin Gupta2016-10-152-130/+0
* SBE compile issue fixedRaja Das2016-10-131-3/+0
* L2 version - p9_sbe_sequence_drtmSantosh2016-10-132-10/+132
* Level 1 HWP - p9_sbe_sequence_drtmSantosh2016-10-132-0/+115
* set TP scan ratio to 8:1 when running on PLLJoe McGill2016-10-131-5/+22
* p9_sbe_chiplet_reset -- adjust scan ratio for chiplets operating at PLL speedJoe McGill2016-10-101-12/+35
* Slowdown after L2cache CE injectSrinivas Naga2016-10-101-1/+12
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