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author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-10-20 08:54:29 +0200 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-10-21 09:58:52 -0400 |
commit | bf064d69540bc66b1e30fed330bace0967c17648 (patch) | |
tree | 602a4d19269030d7e83db5b731e4fc0c3dca779f /src/import/chips/p9/procedures/hwp/perv | |
parent | ea81613efbf1711c0e4c89217efa9bd939af91c0 (diff) | |
download | talos-sbe-bf064d69540bc66b1e30fed330bace0967c17648.tar.gz talos-sbe-bf064d69540bc66b1e30fed330bace0967c17648.zip |
Change clock mux setting to targets PRESENT
Change-Id: Ie0326e0af80f067ce0725bdd0cbb635b915b37fd
CQ:HW391214
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31534
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31539
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 3e61071c..46d1518d 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -646,28 +646,28 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call( l_read_attr)); for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> - (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_PRESENT)) { FAPI_DBG("Mux settings for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC(l_target_cplt, l_read_attr)); } for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> - (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_PRESENT)) { FAPI_DBG("Mux settings for OB chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(l_target_cplt, l_read_attr)); } for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> - (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_PRESENT)) { FAPI_DBG("Mux settings for XB chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_xbus(l_target_cplt, l_read_attr)); } for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> - (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_PRESENT)) { FAPI_DBG("Mux settings for Pcie chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(l_target_cplt, l_read_attr)); |