p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.x

  For DD1.0[123], to obtain Gen3 or Gen4 operation, we need to
  run the PCIE clocks at a slower speed.  For simplicity we will
  just do this across the board for all DD1.0 parts.

  34389 updates the SS filter PLL to output a reduced frequency
  output (94 MHz instead of 100 MHz nominal) for DD1 only.

  This commit will trigger the SBE to use the SS filter PLL to
  feed the downstream PCIE PLLs, for DD1 only.

Change-Id: I344455de1fc54e9180090740b5725d580cb35b6f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34985
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34996
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 27 insertions, 5 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 7dddb7de..8c9fa7ed 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -869,24 +869,46 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
     const fapi2::buffer<uint32_t> i_clk_mux_value)
 {
     uint8_t l_attr_unit_pos = 0;
+    uint8_t l_use_ss_pll = 0;
     fapi2::buffer<uint64_t> l_data64;
     FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ...");
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
                            l_attr_unit_pos));
 
+    // leverage SS filter PLL to feed PCI PLLs, instead of IO filter PLL
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK,
+                           i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(),
+                           l_use_ss_pll));
+
     if ( l_attr_unit_pos != 0x0E )
     {
         //Setting NET_CTRL1 register value
         FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
-        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ?
-                i_clk_mux_value.getBit<5>() :
-                i_clk_mux_value.getBit<4>());  //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() :  i_clk_mux_value.getBit<4>()
+
+        if (l_use_ss_pll)
+        {
+            l_data64.clearBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>();
+        }
+        else
+        {
+            l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ?
+                    i_clk_mux_value.getBit<5>() :
+                    i_clk_mux_value.getBit<4>());  //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() :  i_clk_mux_value.getBit<4>()
+        }
 
         if (l_attr_unit_pos == 0x0D)
         {
-            l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
-            (i_clk_mux_value.getBit<10>());  //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>()
+            if (l_use_ss_pll)
+            {
+                l_data64.setBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>();
+            }
+            else
+            {
+                l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
+                (i_clk_mux_value.getBit<10>());  //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>()
+            }
+
             l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
             (i_clk_mux_value.getBit<11>());  //NET_CTRL1.REFCLK_CLKMUX1_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<11>()
         }