Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | p9_sbe_tp_chiplet_init3: Honor PCI osc selection when checking for osc errors | Joachim Fenkes | 2018-01-12 | 1 | -8/+12 |
* | Fix to skip Osc check in sim only | Soma BhanuTej | 2017-11-02 | 1 | -57/+76 |
* | osclite status check in clock_test2 | Anusha Reddy Rangareddygari | 2017-10-26 | 1 | -10/+28 |
* | p9_sbe_tp_chiplet_init3: Level 3 | Joachim Fenkes | 2017-07-25 | 1 | -1/+1 |
* | Cumulus proc updates | Anusha Reddy Rangareddygari | 2017-07-12 | 1 | -45/+90 |
* | p9_sbe_tp_chiplet_init3: Start PLL SL clocks | Joachim Fenkes | 2017-03-23 | 1 | -2/+12 |
* | p9_sbe_tp_chiplet_init3 | Anusha Reddy Rangareddygari | 2017-03-14 | 1 | -1/+9 |
* | p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulse | Joe McGill | 2017-01-24 | 1 | -3/+13 |
* | p9_sbe_chiplet_reset | Anusha Reddy Rangareddygari | 2017-01-04 | 1 | -2/+2 |
* | Slowdown after L2cache CE inject | Srinivas Naga | 2016-10-10 | 1 | -1/+12 |
* | FFDC Updates | Anusha Reddy Rangareddygari | 2016-09-26 | 1 | -3/+6 |
* | Level 2 HWP for p9_sbe_tp_chiplet_init3 | Anusha Reddy Rangareddygari | 2016-09-21 | 1 | -2/+2 |
* | Changing ATTR_PG from 32 to 16 bit | Anusha Reddy Rangareddygari | 2016-09-21 | 1 | -3/+3 |
* | Removing checkstop checks | Anusha Reddy Rangareddygari | 2016-09-20 | 1 | -12/+0 |
* | FIR updates | Joe McGill | 2016-09-19 | 1 | -2/+2 |
* | Update file headers | Sachin Gupta | 2016-09-16 | 1 | -1/+1 |
* | SBE move import` | Shakeeb | 2016-09-01 | 1 | -0/+371 |