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path: root/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C
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* p9_sbe_tp_chiplet_init3: Mask TOD error bit 62 (osclite switched)Joachim Fenkes2019-02-251-2/+2
* p9_sbe_tp_chiplet_init3: Set up oscillator error mask based on MF osc settingJoachim Fenkes2018-07-041-17/+29
* p9_sbe_tp_chiplet_init3: Don't meddle with osclite controls on CumulusJoachim Fenkes2018-06-261-11/+11
* p9_sbe_tp_chiplet_init3: Honor PCI osc selection when checking for osc errorsJoachim Fenkes2018-01-121-8/+12
* Fix to skip Osc check in sim onlySoma BhanuTej2017-11-021-57/+76
* osclite status check in clock_test2Anusha Reddy Rangareddygari2017-10-261-10/+28
* p9_sbe_tp_chiplet_init3: Level 3Joachim Fenkes2017-07-251-1/+1
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-07-121-45/+90
* p9_sbe_tp_chiplet_init3: Start PLL SL clocksJoachim Fenkes2017-03-231-2/+12
* p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2017-03-141-1/+9
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-241-3/+13
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-01-041-2/+2
* Slowdown after L2cache CE injectSrinivas Naga2016-10-101-1/+12
* FFDC UpdatesAnusha Reddy Rangareddygari2016-09-261-3/+6
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-09-211-2/+2
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-3/+3
* Removing checkstop checksAnusha Reddy Rangareddygari2016-09-201-12/+0
* FIR updatesJoe McGill2016-09-191-2/+2
* Update file headersSachin Gupta2016-09-161-1/+1
* SBE move import`Shakeeb2016-09-011-0/+371
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