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path: root/src/import/chips/p9/procedures/hwp/cache
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* Revert PLL unlock commits of 45102 and 46563Yue Du2017-10-051-3/+0
* {nest,cache}_pll_setup: Properly clear PLL unlock indicationJoachim Fenkes2017-10-041-0/+6
* STOP: Fix MPIPL Dpll Lock via ensuring mode 1Yue Du2017-09-271-1/+9
* PM Level 3 for multiple proceduresAmit Kumar2017-09-202-3/+0
* L3 Update - p9_hcd_cache_stopclocks HWPThi Tran2017-09-174-39/+47
* StopClocks: Fence Refresh region if L3 region clock is stoppedYue Du2017-09-131-1/+17
* PM: Remove VDM check from p9_hcd_cache_stopclocksGreg Still2017-08-221-13/+13
* Synchronous stopclk procedure for QuadSoma BhanuTej2017-08-162-14/+43
* Istep4: procedures upgrade to level3Yue Du2017-07-2030-381/+305
* PM: Delete deprecated attributesGreg Still2017-07-141-4/+4
* Pstate: Remove legacy VDM codeChristopher M. Riedl2017-05-122-15/+5
* Add NCU/L3 dials for HW396230 to p9.ncu.scom.initfileCHRISTINA L. GRAVES2017-04-281-1/+1
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-281-8/+28
* HW404292: Assert analog fence in cache_chiplet_resetYue Du2017-03-312-2/+8
* HW405243/IPL: Assert/drop pcb_mux_disable around quad power offYue Du2017-03-313-6/+61
* update DPLL and IVRM initsJoe McGill2017-03-312-4/+5
* Enablement of additional eq_ana_bndy rings for Nimbus DD2Sumit Kumar2017-03-241-3/+3
* Update quad power off so HB can call it on Slave Quadscrgeddes2017-03-232-16/+16
* Inclusion of p9_ring_id.hKahn Evans2017-03-212-1/+3
* IPL Only: Drop chiplet fence in scomcust instead of startclocksYue Du2017-03-033-69/+47
* Updates to initcompiler to support DD2 and cumulusRichard J. Knight2017-03-011-1/+1
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-02-162-4/+106
* PB Purge Scoms if PBIEQ clock domain is being stoppedRaja Das2017-02-151-2/+53
* HB/IPL: ex_is_abomination workaround for hostbootYue Du2017-02-102-51/+117
* Revert "Hcode: Drop chiplet fence after scominit and scomcust hwp."YUE DU2017-02-093-44/+69
* Hcode: Drop chiplet fence after scominit and scomcust hwp.Yue Du2017-02-063-71/+46
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-01-318-38/+22
* istep 4: only use one EX even if both are goodGreg Still2017-01-191-17/+22
* ISTEP4: using FAPI_ASSERT instead of manual fapi_rc_falseYue Du2017-01-041-38/+33
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-201-7/+13
* IStep4: add check for partial good cores under given exYue Du2016-12-201-29/+38
* p9_hcd_cache_chiplet_reset skip entire vcs workaround in simBen Gass2016-12-201-99/+95
* Istep4: Shouldn't set group_id in cache-contained modeYue Du2016-12-201-7/+11
* Change auto variables to referencesspashabk-in2016-11-224-4/+4
* Fence fixes for L2 loader and Run-N.Ben Gass2016-11-211-0/+32
* STOP Image updatesYue Du2016-11-211-5/+4
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-214-17/+33
* HB: fix HB core boot resulting cme bootYue Du2016-11-101-0/+15
* Istep4: add L3-LCO target setup to cache_scominitYue Du2016-11-091-7/+71
* cache/core/l2_stopclocks updatesYue Du2016-10-262-43/+103
* Skip flushing entire eq ring to 1's in sim p9_hcd_cache_chiplet_resetBen Gass2016-10-211-2/+28
* Cleaned old makefilesSachin Gupta2016-10-152-113/+0
* Lab: DD1 VCS workaround fixYue Du2016-10-143-42/+48
* HW388878 VCS workaroundJoe McGill2016-10-122-2/+2
* Cache HWP: DD1 VCS WorkaroundYue Du2016-10-113-1/+200
* Stop Clocks for MPIPL (Core & Cache(EQ))Raja Das2016-10-061-0/+2
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-4/+1
* Fix for the EKB build failure caused by hcd constantSangeetha T S2016-09-202-2/+4
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-09-204-17/+290
* Level 1 HWP for p9_stopclocksSoma BhanuTej2016-09-202-7/+3
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