diff options
| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-09-16 15:04:09 +0200 |
|---|---|---|
| committer | Santosh S. Puranik <santosh.puranik@in.ibm.com> | 2016-09-21 02:36:17 -0400 |
| commit | 0a62b30ce373bdb8096fc886ce535078696c2cf4 (patch) | |
| tree | dff6260810e6b78f63d27938aa611fc3b8a86c63 /src/import/chips/p9/procedures/hwp/cache | |
| parent | d7b92b5e575f7ed457ce63b6202c704284b676b3 (diff) | |
| download | talos-sbe-0a62b30ce373bdb8096fc886ce535078696c2cf4.tar.gz talos-sbe-0a62b30ce373bdb8096fc886ce535078696c2cf4.zip | |
Changing ATTR_PG from 32 to 16 bit
Change-Id: I346f10136e9621ea06e381cfad2a2b903cb2bd64
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29834
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29836
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/cache')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index fa20765a..a508e448 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -98,7 +98,6 @@ p9_hcd_cache_startclocks( uint8_t l_attr_chip_id = 0; uint8_t l_attr_chip_unit_pos = 0; uint8_t l_attr_system_ipl_phase; - uint32_t l_attr_pg; fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = @@ -113,8 +112,6 @@ p9_hcd_cache_startclocks( l_attr_chip_id)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip, l_attr_system_id)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, l_perv, - l_attr_pg)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos)); l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET; @@ -304,7 +301,7 @@ p9_hcd_cache_startclocks( // Cleaning up // ------------------------------- - if (((~l_attr_pg) & BITS32(4, 11)) && l_attr_system_ipl_phase != 4) + if (l_attr_system_ipl_phase != 4) { FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18))); |
