Istep4: clean up istep4 todo items and mark them with RTC

Change-Id: I6ebe062043fe8d7d036ec5c3a32cf2115fb0fc95
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34689
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34690
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

8 files changed, 22 insertions, 38 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
index 7a1897ef..7599c5c9 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -80,7 +80,7 @@ enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS
     CACHE_GLSMUX_RESET_DELAY_REF_CYCLES = 40
 };
 
-/// @todo RTC 162433
+/// @todo RTC162433 DD2 revisit HW388878
 /// This is going to break on Nimbus DD2.0 and Cumulus SoA testing.
 /// need more discussion in HW/FW interlock on how to handle this.
 enum HW388878_DD1_FIX_CONSTATNS
@@ -158,7 +158,7 @@ p9_hcd_cache_chiplet_reset(
                          MASK_SET(2)));
     }
 
-    /// @todo needs to revisit this sim workaround
+    /// @todo RTC158181 needs to revisit this sim workaround
     FAPI_DBG("Init heartbeat hang counter via HANG_PULSE_6[2]");
     FAPI_TRY(putScom(i_target, EQ_HANG_PULSE_6_REG, MASK_SET(2)));
 
@@ -190,7 +190,7 @@ p9_hcd_cache_chiplet_reset(
     FAPI_DBG("Drop vital thold via NET_CTRL0[16]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16)));
 
-    /// @todo optional setup sector buffer strength, pulse mode and pulsed mode enable
+    /// @todo RTC158181 setup sector buffer strength, pulse mode and pulsed mode enable
 
     FAPI_DBG("Drop cache glsmux reset via PPM_CGCR[0]");
     FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(3)));
@@ -271,13 +271,6 @@ p9_hcd_cache_chiplet_reset(
     }
 #endif
 
-    /// @todo scan_with_setpulse_module(L3 DCC)
-    //FAPI_DBG("Drop L3 DCC bypass via NET_CTRL1[1]");
-    //FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WAND, MASK_UNSET(1)));
-    /// @todo add VDM_ENABLE attribute control
-    //FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]");
-    //FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_OR, MASK_SET(0)));
-
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_chiplet_reset");
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
index 923a4b3d..f4585e5a 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -28,24 +28,16 @@
 ///
 /// Procedure Summary:
 ///   Note:
-///     Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///     Initfiles in procedure defined on VBU ENGD wiki
 ///     DPLL tune bits are not dependent on frequency
 ///     Frequency is controlled by the Quad PPM
 ///       Actual frequency value for boot is stored into the Quad PPM by
 ///         p9_hcd_setup_evid.C in istep 2
 ///       In real cache STOP exit, the frequency value is persistent
 ///
-///   Pre-Scan:
-///
-///   Scan:
-///     (TODO) Set clock controller scan ratio to 1:1 as this is done at refclk
-///     (TODO) scan0 (region = DPLL and ANEP, scan_type = GPTR)
-///     (TODO) scan0 (region = DPLL and ANEP, scan_type = FUNC)
-///     (TODO) Set clock controller scan ratio to 8:1 for future scans
-///
 ///   Setup:
-///     (TODO) set DPLL FREQ CTRL regitster
-///     (TODO) set DPLL CTRL register
+///     @todo  RTC158181 set DPLL FREQ CTRL regitster
+///     (DONE) set DPLL CTRL register
 ///     (Done) Drop DPLL test mode;
 ///     (Done) Drop DPLL into Reset;
 ///     (Done) Start DPLL clock via quad clock controller
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
index 04acb52d..a0858bae 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,7 +27,7 @@
 /// @brief Load GPTR and Time for EX non-core
 ///
 /// Procedure Summary:
-///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///   Initfiles in procedure defined on VBU ENGD wiki
 ///     to produce #G VPD contents
 ///   Check for the presence of core override GPTR ring from image
 ///     (this is new fvor P9)
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
index 3929280f..ce2e5955 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,12 +27,12 @@
 /// @brief EX (non-core) scan init
 ///
 /// Procedure Summary:
-///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///   Initfiles in procedure defined on VBU ENGD wiki
 ///   Check for the presence of cache FUNC override rings from image;
 ///   if found, apply;  if not, apply cache base FUNC rings from image
 ///   Note:  FASTINIT ring (eg CMSK ring) is setup at this point to limit the
 ///   stumps that participate in FUNC ring scanning (this is new for P9).
-///   (TODO to make sure the image build support is in place)
+///   (need to make sure the image build support is in place)
 ///   Note: all caches that are in the Cache Multicast group will be
 ///   initialized to the same values via multicast scans
 
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C
index 198a7034..0b465eb4 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -33,8 +33,7 @@
 /// *HWP Level       : 1
 ///
 /// Procedure Summary:
-///   Run-time updates from OCC code that are put  somewhere TBD
-///     (TODO . revisit with OCC FW team)
+///   Run-time updates from OCC code that are put somewhere revisit with OCC FW team
 ///   OCC FW sets up value in the TBD SCOM section
 ///   This was not leverage in P8 with the demise of CPMs
 ///   Placeholder at this point
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
index ed6fc353..c5b07b37 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -32,7 +32,7 @@
 ///   (Done) Drop partial good regional fences(always drop vital and pervasive)
 ///   (Done) Drop Vital fence
 ///   (Done) Reset abst clock muxsel, sync muxsel
-///   (TODO) Set fabric node/chip ID from the nest version
+///   (DONE) Set fabric node/chip ID from the nest version
 ///   (Done) module align_chiplets
 ///   (Done)  - set flushmode_inh to exit flush mode
 ///   (Done)  - set force align
@@ -319,7 +319,7 @@ p9_hcd_cache_startclocks(
         FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18)));
     }
 
-    /// @todo ignore xstop checkstop in sim, review for lab
+    /// @todo RTC158181 ignore xstop checkstop in sim, review for lab
     /*
     FAPI_DBG("Check the Global Checkstop FIR");
     FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64));
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
index 80680dda..4779f371 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -106,7 +106,7 @@ p9_hcd_cache_stopclocks(
     if (!l_data64.getBit<15>())
     {
         FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
-        /// @todo suspend_pm()
+        /// @todo RTC158181 suspend_pm()
     }
 
     FAPI_DBG("Check cache clock controller status");
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
index c4f0657c..94724da1 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -107,7 +107,7 @@ p9_hcd_l2_stopclocks(
     if (!l_data64.getBit<15>())
     {
         FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
-        /// @todo suspend_pm()
+        /// @todo RTC158181 suspend_pm()
     }
 
     FAPI_DBG("Check cache clock controller status");