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| author | Claus Michael Olsen <cmolsen@us.ibm.com> | 2018-04-09 13:48:56 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-04-24 21:19:15 -0400 |
| commit | 84cfeb2aef7acdb4ce7e7c758faf00b8c6a10fd7 (patch) | |
| tree | acf0c2bd3eafaec4241557b3fd7c7619f8f48b70 /src/import/chips/p9/procedures/xml | |
| parent | c0db49ee81188dbba099b77bd1247d3f09906a22 (diff) | |
| download | talos-sbe-84cfeb2aef7acdb4ce7e7c758faf00b8c6a10fd7.tar.gz talos-sbe-84cfeb2aef7acdb4ce7e7c758faf00b8c6a10fd7.zip | |
Risk level 3/4/5 support: Step 1 - backward compatibility and v6 image
- Introducing RV_RL3/4/5 ring variant (RV) support for EC/EQ chiplets.
- Dropping RV support for all chiplet's instance rings which saves 456
Quad bytes and 58 Nest bytes in Seeprom's TOR slots (compared to
master).
- Each additional risk level adds 144 bytes in Seeprom TOR slots.
- Various changes to data names associated with ring variants to
clarify that the notion of ring variants is now specific only to
Common rings while Instance rings only have the BASE variant.
- Also, removed backwards compatibility to TOR v5, i.e. from before
we introduced RL2 in february. Assumption is that all images/drivers
used in fips910/920 and OP920 are TOR v6.
- This commit produces a TOR v6 image to ensure EKB FSP CI success.
Key_Cronus_Test=XIP_REGRESS
Change-Id: Icfcb1e68fd74a10ffc48ee7a5da528a8042ef3b1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56973
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56982
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rwxr-xr-x | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 51cb1e66..9486f295 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -210,7 +210,7 @@ <description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven HWPs</description> <valueType>uint8</valueType> - <enum>RL0 = 0x0,RL1 = 0x1,RL2 = 0x2</enum> + <enum>RL0 = 0x0,RL1 = 0x1,RL2 = 0x2,RL3 = 0x3,RL4 = 0x4, RL5 = 0x5</enum> <persistRuntime/> <platInit/> </attribute> |
