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author | Joe McGill <jmcgill@us.ibm.com> | 2016-12-29 15:53:03 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-02 21:47:44 -0500 |
commit | 234c3bcaa7cb7dced78d9885be4cebc7ab6b0a3d (patch) | |
tree | f46f4c62b83b4a3249d335fb9437f607e428f8d1 /src/import/chips/p9/procedures/hwp/nest | |
parent | f003212ce80313b66078e39a6d29ae9d60dfcdb9 (diff) | |
download | talos-sbe-234c3bcaa7cb7dced78d9885be4cebc7ab6b0a3d.tar.gz talos-sbe-234c3bcaa7cb7dced78d9885be4cebc7ab6b0a3d.zip |
FIR updates -- pervasive/core/PPE
p9_obus_scom_address_fixes.H
add OBUS IO PPE address constants
p9.cme.scan.initfile
align EQ pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scan.initfile
align EC pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scom.initfile
p9_hcd_core_scominit.c
adjust core FIR action settings for bits 1,12:13 to match RAS XML doc
p9_sbe_scominit.C
mask PBA FIR bit 1 to match RAS XML doc
initialize FBC/XBUS/OBUS PPE FIR registers
p9_sbe_common.C
align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs
CMVC-prereq:1014393
CMVC-prereq:1014431
Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34336
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C | 104 |
1 files changed, 101 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index c339dd3d..7189540b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,6 +49,8 @@ #include <p9_misc_scom_addresses.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> +#include <p9_xbus_scom_addresses.H> +#include <p9_obus_scom_addresses.H> #include <p9_sbe_common.H> @@ -79,7 +81,22 @@ const uint64_t LPC_FIR_MASK = 0x00F0000000000000ULL; // PBA FIR constants const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t PBA_FIR_ACTION1 = 0x0C0100600C000000ULL; -const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL; +const uint64_t PBA_FIR_MASK = 0x7082448062FC0000ULL; + +// PPE FIR constants +// FBC +const uint64_t FBC_PPE_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; +const uint64_t FBC_PPE_FIR_MASK = 0x0E1C000000000000ULL; +// XBUS +const uint64_t XB_PPE_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t XB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; +const uint64_t XB_PPE_FIR_MASK = 0x0E38000000000000ULL; +// OBUS +const uint64_t OB_PPE_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t OB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL; +const uint64_t OB_PPE_FIR_MASK = 0x0E38000000000000ULL; + //------------------------------------------------------------------------------ // Function definitions @@ -319,9 +336,90 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) for (auto& l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>(l_target_filter, fapi2::TARGET_STATE_FUNCTIONAL)) { - + uint8_t l_unit_pos = 0; FAPI_INF("Call p9_sbe_common_configure_chiplet_FIR"); FAPI_TRY(p9_sbe_common_configure_chiplet_FIR(l_chplt_target)); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + + if (l_unit_pos == 0x05) + { + // configure FBC PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRACT0, FBC_PPE_FIR_ACTION0), + "Error from putScom (PU_PB_PPE_LFIRACT0)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRACT1, FBC_PPE_FIR_ACTION1), + "Error from putScom (PU_PB_PPE_LFIRACT1)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRMASK, FBC_PPE_FIR_MASK), + "Error from putScom (PU_PB_PPE_LFIRMASK)"); + } + + if (l_unit_pos == 0x06) + { + // configure XBUS PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_ACTION0_REG, XB_PPE_FIR_ACTION0), + "Error from putScom (XBUS_IOPPE_PPE_FIR_ACTION0_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_ACTION1_REG, XB_PPE_FIR_ACTION1), + "Error from putScom (XBUS_IOPPE_PPE_FIR_ACTION1_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_MASK_REG, XB_PPE_FIR_MASK), + "Error from putScom (XBUS_IOPPE_PPE_FIR_MASK_REG)"); + } + + if (l_unit_pos == 0x09) + { + // configure OBUS0 PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0), + "Error from putScom (OBUS_0_IOPPE_PPE_FIR_ACTION0_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1), + "Error from putScom (OBUS_0_IOPPE_PPE_FIR_ACTION1_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK), + "Error from putScom (OBUS_0_IOPPE_PPE_FIR_MASK_REG)"); + } + + if (l_unit_pos == 0x0A) + { + // configure OBUS1 PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0), + "Error from putScom (OBUS_1_IOPPE_PPE_FIR_ACTION0_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1), + "Error from putScom (OBUS_1_IOPPE_PPE_FIR_ACTION1_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK), + "Error from putScom (OBUS_1_IOPPE_PPE_FIR_MASK_REG)"); + } + + if (l_unit_pos == 0x0B) + { + // configure OBUS2 PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0), + "Error from putScom (OBUS_2_IOPPE_PPE_FIR_ACTION0_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1), + "Error from putScom (OBUS_2_IOPPE_PPE_FIR_ACTION1_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK), + "Error from putScom (OBUS_2_IOPPE_PPE_FIR_MASK_REG)"); + } + + if (l_unit_pos == 0x0C) + { + // configure OBUS3 PPE FIRs + FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0), + "Error from putScom (OBUS_3_IOPPE_PPE_FIR_ACTION0_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1), + "Error from putScom (OBUS_3_IOPPE_PPE_FIR_ACTION1_REG)"); + + FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK), + "Error from putScom (OBUS_3_IOPPE_PPE_FIR_MASK_REG)"); + } } } |