FIR updates -- pervasive/core/PPE

p9_obus_scom_address_fixes.H
  add OBUS IO PPE address constants

p9.cme.scan.initfile
  align EQ pervasive LFIR/XFIR settings with RAS XML docs

p9.core.scan.initfile
  align EC pervasive LFIR/XFIR settings with RAS XML docs

p9.core.scom.initfile
p9_hcd_core_scominit.c
  adjust core FIR action settings for bits 1,12:13 to match RAS XML doc

p9_sbe_scominit.C
  mask PBA FIR bit 1 to match RAS XML doc
  initialize FBC/XBUS/OBUS PPE FIR registers

p9_sbe_common.C
  align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs

CMVC-prereq:1014393
CMVC-prereq:1014431
Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34336
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 178 insertions, 52 deletions

diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H
index 1cadbddf..fb076562 100644
--- a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H
+++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -61,4 +61,32 @@ REG64( OBUS_2_LL2_IOOL_CONTROL,
 REG64( OBUS_2_LL2_LL2_LL2_PB_IOOL_FIR_REG,
        RULL(0x0B010800), SH_UNT_OBUS_2, SH_ACS_SCOM );
 
+REG64( OBUS_0_IOPPE_PPE_FIR_ACTION0_REG,
+       RULL(0x09011046), SH_UNT_OBUS_0, SH_ACS_SCOM );
+REG64( OBUS_0_IOPPE_PPE_FIR_ACTION1_REG,
+       RULL(0x09011047), SH_UNT_OBUS_0, SH_ACS_SCOM );
+REG64( OBUS_0_IOPPE_PPE_FIR_MASK_REG,
+       RULL(0x09011043), SH_UNT_OBUS_0, SH_ACS_SCOM );
+
+REG64( OBUS_1_IOPPE_PPE_FIR_ACTION0_REG,
+       RULL(0x0A011046), SH_UNT_OBUS_1, SH_ACS_SCOM );
+REG64( OBUS_1_IOPPE_PPE_FIR_ACTION1_REG,
+       RULL(0x0A011047), SH_UNT_OBUS_1, SH_ACS_SCOM );
+REG64( OBUS_1_IOPPE_PPE_FIR_MASK_REG,
+       RULL(0x0A011043), SH_UNT_OBUS_1, SH_ACS_SCOM );
+
+REG64( OBUS_2_IOPPE_PPE_FIR_ACTION0_REG,
+       RULL(0x0B011046), SH_UNT_OBUS_2, SH_ACS_SCOM );
+REG64( OBUS_2_IOPPE_PPE_FIR_ACTION1_REG,
+       RULL(0x0B011047), SH_UNT_OBUS_2, SH_ACS_SCOM );
+REG64( OBUS_2_IOPPE_PPE_FIR_MASK_REG,
+       RULL(0x0B011043), SH_UNT_OBUS_2, SH_ACS_SCOM );
+
+REG64( OBUS_3_IOPPE_PPE_FIR_ACTION0_REG,
+       RULL(0x0C011046), SH_UNT_OBUS_3, SH_ACS_SCOM );
+REG64( OBUS_3_IOPPE_PPE_FIR_ACTION1_REG,
+       RULL(0x0C011047), SH_UNT_OBUS_3, SH_ACS_SCOM );
+REG64( OBUS_3_IOPPE_PPE_FIR_MASK_REG,
+       RULL(0x0C011043), SH_UNT_OBUS_3, SH_ACS_SCOM );
+
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C
index 59aababd..80f65383 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C
@@ -31,7 +31,7 @@ using namespace fapi2;
 
 constexpr uint64_t literal_0x0301D70000AB7696 = 0x0301D70000AB7696;
 constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000;
-constexpr uint64_t literal_0xA858009775100008 = 0xA858009775100008;
+constexpr uint64_t literal_0xA854009775100008 = 0xA854009775100008;
 
 fapi2::ReturnCode p9_core_scom(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& TGT0)
 {
@@ -52,7 +52,7 @@ fapi2::ReturnCode p9_core_scom(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& TGT
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x20010a47ull, l_scom_buffer ));
 
-            l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xA858009775100008 );
+            l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xA854009775100008 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x20010a47ull, l_scom_buffer));
         }
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index c339dd3d..7189540b 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -49,6 +49,8 @@
 #include <p9_misc_scom_addresses.H>
 #include <p9_perv_scom_addresses.H>
 #include <p9_perv_scom_addresses_fld.H>
+#include <p9_xbus_scom_addresses.H>
+#include <p9_obus_scom_addresses.H>
 #include <p9_sbe_common.H>
 
 
@@ -79,7 +81,22 @@ const uint64_t LPC_FIR_MASK    = 0x00F0000000000000ULL;
 // PBA FIR constants
 const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL;
 const uint64_t PBA_FIR_ACTION1 = 0x0C0100600C000000ULL;
-const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL;
+const uint64_t PBA_FIR_MASK = 0x7082448062FC0000ULL;
+
+// PPE FIR constants
+// FBC
+const uint64_t FBC_PPE_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t FBC_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL;
+const uint64_t FBC_PPE_FIR_MASK    = 0x0E1C000000000000ULL;
+// XBUS
+const uint64_t XB_PPE_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t XB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL;
+const uint64_t XB_PPE_FIR_MASK    = 0x0E38000000000000ULL;
+// OBUS
+const uint64_t OB_PPE_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t OB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL;
+const uint64_t OB_PPE_FIR_MASK    = 0x0E38000000000000ULL;
+
 
 //------------------------------------------------------------------------------
 // Function definitions
@@ -319,9 +336,90 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         for (auto& l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>(l_target_filter,
                 fapi2::TARGET_STATE_FUNCTIONAL))
         {
-
+            uint8_t l_unit_pos = 0;
             FAPI_INF("Call p9_sbe_common_configure_chiplet_FIR");
             FAPI_TRY(p9_sbe_common_configure_chiplet_FIR(l_chplt_target));
+
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_pos),
+                     "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
+
+            if (l_unit_pos == 0x05)
+            {
+                // configure FBC PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRACT0, FBC_PPE_FIR_ACTION0),
+                         "Error from putScom (PU_PB_PPE_LFIRACT0)");
+
+                FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRACT1, FBC_PPE_FIR_ACTION1),
+                         "Error from putScom (PU_PB_PPE_LFIRACT1)");
+
+                FAPI_TRY(fapi2::putScom(i_target, PU_PB_PPE_LFIRMASK, FBC_PPE_FIR_MASK),
+                         "Error from putScom (PU_PB_PPE_LFIRMASK)");
+            }
+
+            if (l_unit_pos == 0x06)
+            {
+                // configure XBUS PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_ACTION0_REG, XB_PPE_FIR_ACTION0),
+                         "Error from putScom (XBUS_IOPPE_PPE_FIR_ACTION0_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_ACTION1_REG, XB_PPE_FIR_ACTION1),
+                         "Error from putScom (XBUS_IOPPE_PPE_FIR_ACTION1_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, XBUS_IOPPE_PPE_FIR_MASK_REG, XB_PPE_FIR_MASK),
+                         "Error from putScom (XBUS_IOPPE_PPE_FIR_MASK_REG)");
+            }
+
+            if (l_unit_pos == 0x09)
+            {
+                // configure OBUS0 PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0),
+                         "Error from putScom (OBUS_0_IOPPE_PPE_FIR_ACTION0_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1),
+                         "Error from putScom (OBUS_0_IOPPE_PPE_FIR_ACTION1_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_0_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK),
+                         "Error from putScom (OBUS_0_IOPPE_PPE_FIR_MASK_REG)");
+            }
+
+            if (l_unit_pos == 0x0A)
+            {
+                // configure OBUS1 PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0),
+                         "Error from putScom (OBUS_1_IOPPE_PPE_FIR_ACTION0_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1),
+                         "Error from putScom (OBUS_1_IOPPE_PPE_FIR_ACTION1_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_1_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK),
+                         "Error from putScom (OBUS_1_IOPPE_PPE_FIR_MASK_REG)");
+            }
+
+            if (l_unit_pos == 0x0B)
+            {
+                // configure OBUS2 PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0),
+                         "Error from putScom (OBUS_2_IOPPE_PPE_FIR_ACTION0_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1),
+                         "Error from putScom (OBUS_2_IOPPE_PPE_FIR_ACTION1_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_2_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK),
+                         "Error from putScom (OBUS_2_IOPPE_PPE_FIR_MASK_REG)");
+            }
+
+            if (l_unit_pos == 0x0C)
+            {
+                // configure OBUS3 PPE FIRs
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_ACTION0_REG, OB_PPE_FIR_ACTION0),
+                         "Error from putScom (OBUS_3_IOPPE_PPE_FIR_ACTION0_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_ACTION1_REG, OB_PPE_FIR_ACTION1),
+                         "Error from putScom (OBUS_3_IOPPE_PPE_FIR_ACTION1_REG)");
+
+                FAPI_TRY(fapi2::putScom(i_target, OBUS_3_IOPPE_PPE_FIR_MASK_REG, OB_PPE_FIR_MASK),
+                         "Error from putScom (OBUS_3_IOPPE_PPE_FIR_MASK_REG)");
+            }
         }
     }
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
index 327e4fd1..e3a6c601 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -76,60 +76,60 @@ const uint64_t PERV_LFIR_ACTION0[15] =
 
 const uint64_t PERV_LFIR_ACTION1[15] =
 {
-    0x8000000000000000ULL, // TP
-    0x8000000000000000ULL, // N0
-    0x8000000000000000ULL, // N1
-    0x8000000000000000ULL, // N2
-    0x8000000000000000ULL, // N3
-    0x8000000000000000ULL, // X
-    0x8000000000000000ULL, // MC0
-    0x8000000000000000ULL, // MC1
-    0x8000000000000000ULL, // OB0
-    0x8000000000000000ULL, // OB1
-    0x8000000000000000ULL, // OB2
-    0x8000000000000000ULL, // OB3
-    0x8000000000000000ULL, // PCI0
-    0x8000000000000000ULL, // PCI1
-    0x8000000000000000ULL  // PCI2
+    0xF000000000000000ULL, // TP
+    0xF000000000000000ULL, // N0
+    0xF000000000000000ULL, // N1
+    0xF000000000000000ULL, // N2
+    0xF000000000000000ULL, // N3
+    0xF000000000000000ULL, // X
+    0xF000000000000000ULL, // MC0
+    0xF000000000000000ULL, // MC1
+    0xF000000000000000ULL, // OB0
+    0xF000000000000000ULL, // OB1
+    0xF000000000000000ULL, // OB2
+    0xF000000000000000ULL, // OB3
+    0xF000000000000000ULL, // PCI0
+    0xF000000000000000ULL, // PCI1
+    0xF000000000000000ULL  // PCI2
 };
 
 const uint64_t PERV_LFIR_MASK[15] =
 {
-    0xFFFFFFFFFFC00000ULL, // TP
-    0xFFFFFFFFFFC00000ULL, // N0
-    0xFFFFFFFFFFC00000ULL, // N1
-    0xFFFFFFFFFFC00000ULL, // N2
-    0xFFFFFFFFFFC00000ULL, // N3
-    0xFFFFFFFFFFC00000ULL, // X
-    0xFFFFFFFFFFC00000ULL, // MC0
-    0xFFFFFFFFFFC00000ULL, // MC1
-    0xFFFFFFFFFFC00000ULL, // OB0
-    0xFFFFFFFFFFC00000ULL, // OB1
-    0xFFFFFFFFFFC00000ULL, // OB2
-    0xFFFFFFFFFFC00000ULL, // OB3
-    0xFFFFFFFFFFC00000ULL, // PCI0
-    0xFFFFFFFFFFC00000ULL, // PCI1
-    0xFFFFFFFFFFC00000ULL  // PCI2
+    0x0FFFBC2BFC400000ULL, // TP
+    0x0FFFFFFFFFC00000ULL, // N0
+    0x0FFFFFFFFFC00000ULL, // N1
+    0x0FFFFFFFFFC00000ULL, // N2
+    0x0FFFFFFF1FC00000ULL, // N3
+    0x0FFFFFFFFFC00000ULL, // X
+    0x0FFFFFFFFFC00000ULL, // MC0
+    0x0FFFFFFFFFC00000ULL, // MC1
+    0x0FFFFFFFFFC00000ULL, // OB0
+    0x0FFFFFFFFFC00000ULL, // OB1
+    0x0FFFFFFFFFC00000ULL, // OB2
+    0x0FFFFFFFFFC00000ULL, // OB3
+    0x0FFFFFFFFFC00000ULL, // PCI0
+    0x0FFFFFFFFFC00000ULL, // PCI1
+    0x0FFFFFFFFFC00000ULL  // PCI2
 };
 
 // chiplet XIR constants
 const uint64_t PERV_XFIR_MASK[15] =
 {
-    0x9FFFFFE000000000ULL, // TP
-    0x2007FFE000000000ULL, // N0
-    0x201FFFE000000000ULL, // N1
-    0x200FFFE000000000ULL, // N2
-    0x000007E000000000ULL, // N3
-    0x210FFFE000000000ULL, // X
-    0x20007FE000000000ULL, // MC0
-    0x20007FE000000000ULL, // MC1
-    0x29FFFFE000000000ULL, // OB0
-    0x29FFFFE000000000ULL, // OB1
-    0x29FFFFE000000000ULL, // OB2
-    0x29FFFFE000000000ULL, // OB3
-    0x21FFFFE000000000ULL, // PCI0
-    0x207FFFE000000000ULL, // PCI1
-    0x201FFFE000000000ULL  // PCI2
+    0x0000000000000000ULL, // TP
+    0x0000000000000000ULL, // N0
+    0x0000000000000000ULL, // N1
+    0x0000000000000000ULL, // N2
+    0x0000000000000000ULL, // N3
+    0x0000000000000000ULL, // X
+    0x0000000000000000ULL, // MC0
+    0x0000000000000000ULL, // MC1
+    0x0000000000000000ULL, // OB0
+    0x0000000000000000ULL, // OB1
+    0x0000000000000000ULL, // OB2
+    0x0000000000000000ULL, // OB3
+    0x0000000000000000ULL, // PCI0
+    0x0000000000000000ULL, // PCI1
+    0x0000000000000000ULL  // PCI2
 };
 
 /// @brief --For all chiplets exit flush