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| author | Yue Du <daviddu@us.ibm.com> | 2016-10-24 10:59:37 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-21 20:47:45 -0500 |
| commit | 04747ee5bdf29a9550b7c7561da72971baef8ca1 (patch) | |
| tree | 19cf96cde6c6642b58e2f4679ff951530a6fc7cf /src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C | |
| parent | 4c58fa5fbe53f9c80972a53c79f0b74f1cadfc79 (diff) | |
| download | talos-sbe-04747ee5bdf29a9550b7c7561da72971baef8ca1.tar.gz talos-sbe-04747ee5bdf29a9550b7c7561da72971baef8ca1.zip | |
Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup
changes in this commit:
1) enable dpll lock checking in non-sim envrionment
2) change FAPI_DBG lines on set/reset sdis_n ops as
removing prints saying they are DD1 only workaround
due to they are permenant steps now
3) add missing content of p9_hcd_core_dcc_skewadjust
4) add DD2 sram_enable support (NOOP for DD1)
Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719
Reviewed-by: Joseph E. Dery <dery@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C index a4ad100b..fa550729 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -222,6 +222,9 @@ p9_hcd_cache_chiplet_reset( FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25))); + FAPI_DBG("Assert sram_enable via NET_CTRL0[23]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(23))); + FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]"); FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); l_data64.insertFromRight<47, 5>(0x0); |
