Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup

changes in this commit:

1) enable dpll lock checking in non-sim envrionment
2) change FAPI_DBG lines on set/reset sdis_n ops as
   removing prints saying they are DD1 only workaround
   due to they are permenant steps now
3) add missing content of p9_hcd_core_dcc_skewadjust
4) add DD2 sram_enable support (NOOP for DD1)

Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719
Reviewed-by: Joseph E. Dery <dery@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

12 files changed, 106 insertions, 37 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
index 683d89ea..d06e3e86 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
@@ -101,8 +101,7 @@ p9_hcd_cache_arrayinit(
         l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
     }
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_OR, MASK_SET(34)));
 
 #ifndef P9_HCD_STOP_SKIP_ARRAYINIT
@@ -135,8 +134,7 @@ p9_hcd_cache_arrayinit(
 
 #endif
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_CLEAR, MASK_SET(34)));
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
index a4ad100b..fa550729 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
@@ -222,6 +222,9 @@ p9_hcd_cache_chiplet_reset(
     FAPI_DBG("Drop PCB fence via NET_CTRL0[25]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25)));
 
+    FAPI_DBG("Assert sram_enable via NET_CTRL0[23]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(23)));
+
     FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]");
     FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
     l_data64.insertFromRight<47, 5>(0x0);
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
index 684161c2..923a4b3d 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
@@ -97,8 +97,16 @@ p9_hcd_cache_dpll_setup(
     fapi2::buffer<uint64_t>                  l_data64;
     uint8_t                                  l_dpll_bypass;
     uint32_t                                 l_timeout;
-
     auto l_parent_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+#ifndef __PPE__
+    uint8_t                                  l_attr_is_simulation;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION,
+                           fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                           l_attr_is_simulation));
+#endif
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, l_parent_chip, l_dpll_bypass),
              "Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS)");
 
@@ -119,8 +127,8 @@ p9_hcd_cache_dpll_setup(
         FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0)));
     }
 
-    FAPI_DBG("Drop DPLL clock region fence via NET_CTRL1[14]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(14)));
+    FAPI_DBG("Drop ANEP+DPLL clock region fences via NET_CTRL1[10, 14]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_CLR(10, 5, 0x11)));
 
     // ----------------
     // Start DPLL clock
@@ -168,8 +176,22 @@ p9_hcd_cache_dpll_setup(
         do
         {
             FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64));
-            ///@todo disable poll for DPLL lock until model setting in place
+
+#ifndef __PPE__
+
+            if (l_attr_is_simulation)
+            {
+                FAPI_DBG("Skipping DPLL lock check in Sim");
+                break;
+            }
+
+#else
+#ifdef SIM_DPLL_LOCK_CHK
+            FAPI_DBG("Skipping DPLL lock check in Sim");
             break;
+#endif
+#endif
+
         }
         while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0));
 
@@ -182,7 +204,6 @@ p9_hcd_cache_dpll_setup(
         FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]");
         FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5)));
 
-
         FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
         FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
     }
@@ -202,15 +223,9 @@ p9_hcd_cache_dpll_setup(
         FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
     }
 
-    FAPI_DBG("Drop ANEP clock region fence via CPLT_CTRL1[10]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10)));
-
     FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(22)));
 
-    FAPI_DBG("Drop skew adjust reset via NET_CTRL0[2]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(2)));
-
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_dpll_setup");
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
index 01c793e6..81cf5ebe 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
@@ -131,7 +131,7 @@ p9_hcd_cache_startclocks(
     // 0x0 -> 0x8 -> 0xC -> 0xE -> 0xF to turn on edram
     // stagger EDRAM turn-on per EX (not both at same time)
 
-    l_region_clock = p9hcd::CLK_REGION_ALL_BUT_EX_ANEP_DPLL;
+    l_region_clock = p9hcd::CLK_REGION_ALL_BUT_EX_DPLL;
     l_l2sync_clock = 0;
     l_l2pscom_mask = 0;
     l_l3pscom_mask = 0;
@@ -306,7 +306,7 @@ p9_hcd_cache_startclocks(
     // Cleaning up
     // -------------------------------
 
-    if (l_attr_system_ipl_phase != 4)
+    if (l_attr_system_ipl_phase != fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
     {
         FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]");
         FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18)));
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
index 6145ad1a..47780ffb 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
@@ -75,8 +75,7 @@ p9_hcd_core_arrayinit(
         i_target.getParent<fapi2::TARGET_TYPE_PERV>();
 #endif
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
 
 #ifndef P9_HCD_STOP_SKIP_ARRAYINIT
@@ -109,8 +108,7 @@ p9_hcd_core_arrayinit(
 
 #endif
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
 
 //#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
index e589933b..f4bf3ba6 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
@@ -191,6 +191,14 @@ p9_hcd_core_chiplet_reset(
     FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]");
     FAPI_TRY(putScom(i_target, C_PPM_VDMCR_OR, MASK_SET(0)));
 
+    // content of p9_hcd_core_dcc_skewadjust below:
+
+    FAPI_DBG("Drop core DCC bypass via NET_CTRL[1]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL1_WAND, MASK_UNSET(1)));
+
+    FAPI_DBG("Drop core progdly bypass(skewadjust) via NET_CTRL1[2]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL1_WAND, MASK_UNSET(2)));
+
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_core_chiplet_reset");
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
index c44e6a4d..deafdd57 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
@@ -93,6 +93,7 @@ p9_hcd_core_startclocks(
     uint8_t                                     l_attr_chip_unit_pos;
     uint8_t                                     l_attr_system_ipl_phase;
     uint8_t                                     l_attr_runn_mode;
+    uint8_t                                     l_attr_sdisn_setup;
     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
         i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
     fapi2::Target<fapi2::TARGET_TYPE_EQ>        l_quad =
@@ -101,16 +102,21 @@ p9_hcd_core_startclocks(
         i_target.getParent<fapi2::TARGET_TYPE_PERV>();
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
+                           l_attr_sdisn_setup));
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,        l_chip,
+                           l_attr_group_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,         l_chip,
+                           l_attr_chip_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID,       l_chip,
+                           l_attr_system_id));
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE,        l_sys,
                            l_attr_runn_mode));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys,
                            l_attr_system_ipl_phase));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,  l_chip,
-                           l_attr_group_id));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,   l_chip,
-                           l_attr_chip_id));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip,
-                           l_attr_system_id));
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,    l_perv,
                            l_attr_chip_unit_pos));
     l_attr_chip_unit_pos = (l_attr_chip_unit_pos -
@@ -127,9 +133,11 @@ p9_hcd_core_startclocks(
         FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5)));
     }
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
-    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+    if (l_attr_sdisn_setup)
+    {
+        FAPI_DBG("DD1 ONLY: Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
+        FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+    }
 
     FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
     FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64));
@@ -284,10 +292,7 @@ p9_hcd_core_startclocks(
                          EX_0_CME_SCOM_SICR_CLEAR : EX_1_CME_SCOM_SICR_CLEAR,
                          (BIT64(6 + (l_attr_chip_unit_pos % 2)) |
                           BIT64(8 + (l_attr_chip_unit_pos % 2)))));
-    }
 
-    if (!l_attr_runn_mode)
-    {
         FAPI_DBG("Drop auto special wakeup disable via CME_SCOM_LMCR[12/13]");
         FAPI_TRY(putScom(l_quad,
                          (l_attr_chip_unit_pos < 2) ?
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
index 1aaa7cd5..54805273 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
@@ -75,9 +75,14 @@ p9_hcd_core_stopclocks(
     uint32_t                                       l_loops1ms;
     uint8_t                                        l_attr_chip_unit_pos;
     uint8_t                                        l_attr_vdm_enable;
+    uint8_t                                        l_attr_sdisn_setup;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     auto  l_quad = i_target.getParent<fapi2::TARGET_TYPE_EQ>();
     auto  l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto  l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
+                           l_attr_sdisn_setup));
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,       l_sys,
                            l_attr_vdm_enable));
@@ -221,9 +226,11 @@ p9_hcd_core_stopclocks(
     FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]");
     FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_OR, p9hcd::CLK_REGION_ALL));
 
-    /// @todo RTC158181 add DD1 attribute control
-    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
-    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
+    if (l_attr_sdisn_setup)
+    {
+        FAPI_DBG("DD1 Only: Drop sdis_n(flushing LCBES condition) vai CPLT_CONF0[34]");
+        FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
+    }
 
     // -------------------------------
     // Disable VDM
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C
index e36da6b9..97be7060 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C
@@ -56,6 +56,10 @@ fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const
 
     FAPI_DBG("Entering ...");
 
+    FAPI_DBG("Release Skew Adjust Reset");
+    l_data64.flush<1>().clearBit<2>();
+    FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL0_WAND, l_data64));
+
     FAPI_DBG("Release L2-0, L2-1 DC Adjust reset");
     l_data64.flush<1>();
     l_data64.clearBit<23>();
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index d100f445..02e1a29d 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -183,6 +183,24 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Sdis_n set or clear : flushing LCBES condition woraround. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** --> 
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW388878</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 5b6fdf55..7d51583f 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -525,7 +525,10 @@ attribute tank
            <name>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</name>
            <virtual/>
   </entry>
-
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</name>
+           <virtual/>
+  </entry>
   <entry>
            <name>ATTR_CHIP_EC_FEATURE_HW388878</name>
            <virtual/>
diff --git a/src/import/chips/p9/sw_simulation/powermgmt.act b/src/import/chips/p9/sw_simulation/powermgmt.act
index 3542457e..0ed178df 100644
--- a/src/import/chips/p9/sw_simulation/powermgmt.act
+++ b/src/import/chips/p9/sw_simulation/powermgmt.act
@@ -19,6 +19,16 @@ CAUSE_EFFECT {
   EFFECT: TARGET=[REG(0x10030008)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0FFE0000 00000000)] DATA=[LITERAL(64,00000000 00000000)]
 }
 
+##
+# Actions for Procedure - p9_hcd_cache_dpll_setup
+##
+
+CAUSE_EFFECT {
+  LABEL=[Start DPLL clock via CLK_REGION]
+  WATCH=[REG(0x10030006)]
+  CAUSE: TARGET=[REG(0x10030006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,40020000 0000E000)]
+  EFFECT: TARGET=[REG(0x100F0155)] OP=[BIT,ON] BIT=[63]
+}
 
 ##
 ## Actions for Procedure - p9_hcd_core_startclocks