diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2016-07-12 23:44:38 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-07-20 23:14:00 -0400 |
| commit | 1360676bf7e29b88614ecdd38e78b3657ceeaabc (patch) | |
| tree | 9d748c3ec4df8ac4d1f09ada761bee71b897b51e /import/chips | |
| parent | 346fe8219631d5caea613514d66570b25eaa3639 (diff) | |
| download | talos-sbe-1360676bf7e29b88614ecdd38e78b3657ceeaabc.tar.gz talos-sbe-1360676bf7e29b88614ecdd38e78b3657ceeaabc.zip | |
VBU IPL -- update sim PLL configuration
Adjust refclock/PLL configuration to drive all mesh clocks from PLLs
non-IO/wafer configuration (nest PLL bucket #1) -- default for sc/sq/fc
IO/system model configuration (nest PLL bucket #2) -- default for mc
Regression framework updates
Remove dependence on sim-only varosc/refclock HWPs
Scan from HW image (ultimately need to move to SEEPROM)
Add memory attribute HWPs missing from flow
Handle real/broadside scan options
HWP updates
Scan PLL configuration from image
Preserve clock mux attribute programming
First crack at removing unneeded PLL buckets from images/TOR
Add boot support for warm IPL
Change-Id: Ic7f27ab3dfdf258471d91618adc8eae4cadb2e42
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26938
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26990
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips')
6 files changed, 706 insertions, 884 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C index 80e757db..8e3b8723 100644 --- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -55,19 +55,10 @@ p9_hcd_cache_dpll_initf( { FAPI_INF(">>p9_hcd_cache_dpll_initf"); -#ifndef P9_HCD_STOP_SKIP_SCAN - FAPI_DBG("Scanning Cache DPLL FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func, - fapi2::RING_MODE_HEADER_CHECK)); + FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func)); fapi_try_exit: - -#endif - FAPI_INF("<<p9_hcd_cache_dpll_initf"); return fapi2::current_err; } - - - diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C index 2f6fb092..77188188 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,93 +32,84 @@ //## auto_generated #include "p9_sbe_chiplet_pll_initf.H" - -#include "p9_perv_sbe_cmn.H" - - -enum P9_SBE_CHIPLET_PLL_INITF_Private_Constants -{ - REGIONS_PLL_ONLY = 0x001, - SCAN_TYPES_GPTR = 0x200, - SCAN_TYPES_BNDY_FUNC = 0x808 -}; +#include "p9_perv_scom_addresses.H" fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { - uint8_t l_read_attr = 0; - auto l_perv_functional_vector = - i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> - (fapi2::TARGET_STATE_FUNCTIONAL); - FAPI_DBG("Entering ..."); + FAPI_INF("Entering ..."); - FAPI_INF("Switch MC meshs to Nest mesh"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); - - if ( l_read_attr ) + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL)) { - for (auto l_chplt_trgt : l_perv_functional_vector) + uint8_t l_unit_pos; + RingID l_ring_id = xb_pll_bndy; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + + switch (l_unit_pos) { - uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, - l_attr_chip_unit_pos)); - - if (!((l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A - || l_attr_chip_unit_pos == 0x0B - || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || - (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E - || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || - (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) - { - continue; - } - - FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, - SCAN_TYPES_GPTR)); - - FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, - SCAN_TYPES_BNDY_FUNC)); - - //TODO:Load Ring Module : Scan initialize PLL BNDY chain + case 0x6: + FAPI_DBG("Scan XBUS chiplet ring"); + l_ring_id = xb_pll_bndy; + break; + + case 0x9: + FAPI_DBG("Scan OB0 chiplet ring"); + l_ring_id = ob0_pll_bndy; + break; + + case 0xa: + FAPI_DBG("Scan OB1 chiplet ring"); + l_ring_id = ob1_pll_bndy; + break; + + case 0xb: + FAPI_DBG("Scan OB2 chiplet ring"); + l_ring_id = ob2_pll_bndy; + break; + + case 0xc: + FAPI_DBG("Scan OB3 chiplet ring"); + l_ring_id = ob3_pll_bndy; + break; + + case 0xd: + FAPI_DBG("Scan PCI0 chiplet ring"); + l_ring_id = pci0_pll_bndy; + break; + + case 0xe: + FAPI_DBG("Scan PCI1 chiplet ring"); + l_ring_id = pci1_pll_bndy; + break; + + case 0xf: + FAPI_DBG("Scan PCI2 chiplet ring"); + l_ring_id = pci2_pll_bndy; + break; + + default: + FAPI_ASSERT(false, + fapi2::P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET(). + set_TARGET(l_chplt_trgt). + set_UNIT_POS(l_unit_pos), + "Unexpected chiplet!"); } + + FAPI_TRY(fapi2::putRing(i_target_chip, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL)); + } - else + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) { - for (auto l_chplt_trgt : l_perv_functional_vector) - { - uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, - l_attr_chip_unit_pos)); - - if (!((l_attr_chip_unit_pos == 0x07 - || l_attr_chip_unit_pos == 0x08/* McChiplet */) || - (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A - || l_attr_chip_unit_pos == 0x0B - || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || - (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E - || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || - (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) - { - continue; - } - - FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, - SCAN_TYPES_GPTR)); - - FAPI_INF("Call Scan0 Module (scan region=PLL, scan types=GPTR)"); - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_chplt_trgt, REGIONS_PLL_ONLY, - SCAN_TYPES_BNDY_FUNC)); - - //TODO:Load Ring Module : Scan initialize PLL BNDY chain - } + FAPI_DBG("Scan initialize MC chiplet ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL)); } - FAPI_DBG("Exiting ..."); - fapi_try_exit: + FAPI_INF("Exiting ..."); return fapi2::current_err; - } diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C index d4371a7b..2a8399c3 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C @@ -36,17 +36,17 @@ fapi2::ReturnCode p9_sbe_npll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { + FAPI_INF("Entering ..."); + uint8_t l_read_attr = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; RingID ringID = perv_pll_bndy_bucket_1; - FAPI_INF("Entering ..."); - FAPI_DBG("Get the attribute ATTR_NEST_PLL_BUCKET"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_read_attr)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_read_attr), + "Error from FAPI_ATTR_GET (ATTR_NEST_PLL_BUCKET)"); switch(l_read_attr) { - case 1: ringID = perv_pll_bndy_bucket_1; break; @@ -68,13 +68,16 @@ fapi2::ReturnCode p9_sbe_npll_initf(const break; default: - FAPI_TRY(!(fapi2::FAPI2_RC_SUCCESS), "Invalid values of ATTR_NEST_PLL_BUCKET") + FAPI_ASSERT(false, + fapi2::P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET(). + set_TARGET(i_target_chip). + set_BUCKET_INDEX(l_read_attr), + "Unsupported Nest PLL bucket value!"); } FAPI_TRY(fapi2::putRing(i_target_chip, ringID, fapi2::RING_MODE_SET_PULSE_NSL)); - FAPI_INF("Exiting ..."); - fapi_try_exit: + FAPI_INF("Exiting ..."); return fapi2::current_err; } diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml index 7ea07e36..8f7d2dc3 100755 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml @@ -18,4 +18,12 @@ <!-- IBM_PROLOG_END_TAG --> <!-- Halt codes for p9_sbe_chiplet_pll_initf --> <hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET</rc> + <description>Unsupported/unexpected pervasive chiplet instance</description> + <ffdc>TARGET</ffdc> + <ffdc>UNIT_POS</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml b/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml index cd74795b..28012297 100755 --- a/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml +++ b/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml @@ -18,4 +18,12 @@ <!-- IBM_PROLOG_END_TAG --> <!-- Halt codes for p9_sbe_npll_initf --> <hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET</rc> + <description>Unsupported Nest PLL bucket value</description> + <ffdc>TARGET</ffdc> + <ffdc>BUCKET_INDEX</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/import/chips/p9/utils/imageProcs/p9_ringId.H b/import/chips/p9/utils/imageProcs/p9_ringId.H index e6c4b11a..3b50870f 100644 --- a/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -164,218 +164,189 @@ enum RingID xb_io2_time = 86, xb_pll_gptr = 87, xb_pll_bndy = 88, - xb_pll_bndy_bucket_1 = 89, - xb_pll_bndy_bucket_2 = 90, - xb_pll_bndy_bucket_3 = 91, - xb_pll_bndy_bucket_4 = 92, - xb_pll_bndy_bucket_5 = 93, - xb_pll_func = 94, + xb_pll_func = 89, // X-Bus Chiplet Rings // X0, X1 and X2 instance specific Rings - xb_repr = 95, - xb_io0_repr = 96, - xb_io1_repr = 97, - xb_io2_repr = 98, - // values 99 unused - // values 100 unused + xb_repr = 90, + xb_io0_repr = 91, + xb_io1_repr = 92, + xb_io2_repr = 93, + // values 94-95 unused // MC Chiplet Rings // Common - apply to all instances of MC - mc_fure = 101, - mc_gptr = 102, - mc_time = 103, - mc_iom01_fure = 104, - mc_iom01_gptr = 105, - mc_iom01_time = 106, - mc_iom23_fure = 107, - mc_iom23_gptr = 108, - mc_iom23_time = 109, - mc_pll_gptr = 110, - mc_pll_bndy = 111, - mc_pll_bndy_bucket_1 = 112, - mc_pll_bndy_bucket_2 = 113, - mc_pll_bndy_bucket_3 = 114, - mc_pll_bndy_bucket_4 = 115, - mc_pll_bndy_bucket_5 = 116, - mc_pll_func = 117, + mc_fure = 96, + mc_gptr = 97, + mc_time = 98, + mc_iom01_fure = 99, + mc_iom01_gptr = 100, + mc_iom01_time = 101, + mc_iom23_fure = 102, + mc_iom23_gptr = 103, + mc_iom23_time = 104, + mc_pll_gptr = 105, + mc_pll_bndy = 106, + mc_pll_bndy_bucket_1 = 107, + mc_pll_bndy_bucket_2 = 108, + mc_pll_bndy_bucket_3 = 109, + mc_pll_bndy_bucket_4 = 110, + mc_pll_bndy_bucket_5 = 111, + mc_pll_func = 112, // MC Chiplet Rings // MC01 and MC23 instance specific Rings - mc_repr = 118, - mc_iom01_repr = 119, - mc_iom23_repr = 120, - // values 121-122 unused + mc_repr = 113, + mc_iom01_repr = 114, + mc_iom23_repr = 115, + // values 116-117 unused // OB Chiplet Rings // Common - apply to all instances of O-Bus - ob0_fure = 123, - ob0_gptr = 124, - ob0_time = 125, - ob0_pll_gptr = 126, - ob0_pll_bndy = 127, - ob0_pll_bndy_bucket_1 = 128, - ob0_pll_bndy_bucket_2 = 129, - ob0_pll_bndy_bucket_3 = 130, - ob0_pll_bndy_bucket_4 = 131, - ob0_pll_bndy_bucket_5 = 132, - ob0_pll_func = 133, + ob0_fure = 118, + ob0_gptr = 119, + ob0_time = 120, + ob0_pll_gptr = 121, + ob0_pll_bndy = 122, + ob0_pll_func = 123, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob0_repr = 134, - // values 135-136 unused - - ob1_fure = 137, - ob1_gptr = 138, - ob1_time = 139, - ob1_pll_gptr = 140, - ob1_pll_bndy = 141, - ob1_pll_bndy_bucket_1 = 142, - ob1_pll_bndy_bucket_2 = 143, - ob1_pll_bndy_bucket_3 = 144, - ob1_pll_bndy_bucket_4 = 145, - ob1_pll_bndy_bucket_5 = 146, - ob1_pll_func = 147, + ob0_repr = 124, + // values 125-126 unused + + ob1_fure = 127, + ob1_gptr = 128, + ob1_time = 129, + ob1_pll_gptr = 130, + ob1_pll_bndy = 131, + ob1_pll_func = 132, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob1_repr = 148, - // values 149-150 unused - - - ob2_fure = 151, - ob2_gptr = 152, - ob2_time = 153, - ob2_pll_gptr = 154, - ob2_pll_bndy = 155, - ob2_pll_bndy_bucket_1 = 156, - ob2_pll_bndy_bucket_2 = 157, - ob2_pll_bndy_bucket_3 = 158, - ob2_pll_bndy_bucket_4 = 159, - ob2_pll_bndy_bucket_5 = 160, - ob2_pll_func = 161, + ob1_repr = 133, + // values 134-135 unused + + ob2_fure = 136, + ob2_gptr = 137, + ob2_time = 138, + ob2_pll_gptr = 139, + ob2_pll_bndy = 140, + ob2_pll_func = 141, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob2_repr = 162, - // values 163-164 unused - - - ob3_fure = 165, - ob3_gptr = 166, - ob3_time = 167, - ob3_pll_gptr = 168, - ob3_pll_bndy = 169, - ob3_pll_bndy_bucket_1 = 170, - ob3_pll_bndy_bucket_2 = 171, - ob3_pll_bndy_bucket_3 = 172, - ob3_pll_bndy_bucket_4 = 173, - ob3_pll_bndy_bucket_5 = 174, - ob3_pll_func = 175, + ob2_repr = 142, + // values 143-144 unused + + ob3_fure = 145, + ob3_gptr = 146, + ob3_time = 147, + ob3_pll_gptr = 148, + ob3_pll_bndy = 149, + ob3_pll_func = 150, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob3_repr = 176, - // value177-178 unused - + ob3_repr = 151, + // values 152-153 unused // PCI Chiplet Rings // PCI0 Common Rings - pci0_fure = 179, - pci0_gptr = 180, - pci0_time = 181, - pci0_pll_func = 182, - pci0_pll_gptr = 183, + pci0_fure = 154, + pci0_gptr = 155, + pci0_time = 156, + pci0_pll_bndy = 157, + pci0_pll_gptr = 158, // Instance specific Rings - pci0_repr = 184, + pci0_repr = 159, // PCI1 Common Rings - pci1_fure = 185, - pci1_gptr = 186, - pci1_time = 187, - pci1_pll_func = 188, - pci1_pll_gptr = 189, + pci1_fure = 160, + pci1_gptr = 161, + pci1_time = 162, + pci1_pll_bndy = 163, + pci1_pll_gptr = 164, // Instance specific Rings - pci1_repr = 190, + pci1_repr = 165, // PCI2 Common Rings - pci2_fure = 191, - pci2_gptr = 192, - pci2_time = 193, - pci2_pll_func = 194, - pci2_pll_gptr = 195, + pci2_fure = 166, + pci2_gptr = 167, + pci2_time = 168, + pci2_pll_bndy = 169, + pci2_pll_gptr = 170, // Instance specific Rings - pci2_repr = 196, + pci2_repr = 171, // Quad Chiplet Rings // Common - apply to all Quad instances - eq_fure = 197, - eq_gptr = 198, - eq_time = 199, - eq_mode = 200, - ex_l3_fure = 201, - ex_l3_gptr = 202, - ex_l3_time = 203, - ex_l2_mode = 204, - ex_l2_fure = 205, - ex_l2_gptr = 206, - ex_l2_time = 207, - ex_l3_refr_fure = 208, - ex_l3_refr_gptr = 209, - ex_l3_refr_time = 210, - eq_ana_func = 211, - eq_ana_gptr = 212, - eq_dpll_func = 213, - eq_dpll_gptr = 214, - eq_dpll_mode = 215, - eq_ana_bndy = 216, - eq_ana_bndy_bucket_0 = 217, - eq_ana_bndy_bucket_1 = 218, - eq_ana_bndy_bucket_2 = 219, - eq_ana_bndy_bucket_3 = 220, - eq_ana_bndy_bucket_4 = 221, - eq_ana_bndy_bucket_5 = 222, - eq_ana_bndy_bucket_6 = 223, - eq_ana_bndy_bucket_7 = 224, - eq_ana_bndy_bucket_8 = 225, - eq_ana_bndy_bucket_9 = 226, - eq_ana_bndy_bucket_10 = 227, - eq_ana_bndy_bucket_11 = 228, - eq_ana_bndy_bucket_12 = 229, - eq_ana_bndy_bucket_13 = 230, - eq_ana_bndy_bucket_14 = 231, - eq_ana_bndy_bucket_15 = 232, - eq_ana_bndy_bucket_16 = 233, - eq_ana_bndy_bucket_17 = 234, - eq_ana_bndy_bucket_18 = 235, - eq_ana_bndy_bucket_19 = 236, - eq_ana_bndy_bucket_20 = 237, - eq_ana_bndy_bucket_21 = 238, - eq_ana_bndy_bucket_22 = 239, - eq_ana_bndy_bucket_23 = 240, - eq_ana_bndy_bucket_24 = 241, - eq_ana_bndy_bucket_25 = 242, - eq_ana_bndy_l3dcc_bucket_26 = 243, - eq_ana_mode = 244, + eq_fure = 172, + eq_gptr = 173, + eq_time = 174, + eq_mode = 175, + ex_l3_fure = 176, + ex_l3_gptr = 177, + ex_l3_time = 178, + ex_l2_mode = 179, + ex_l2_fure = 180, + ex_l2_gptr = 181, + ex_l2_time = 182, + ex_l3_refr_fure = 183, + ex_l3_refr_gptr = 184, + ex_l3_refr_time = 185, + eq_ana_func = 186, + eq_ana_gptr = 187, + eq_dpll_func = 188, + eq_dpll_gptr = 189, + eq_dpll_mode = 190, + eq_ana_bndy = 191, + eq_ana_bndy_bucket_0 = 192, + eq_ana_bndy_bucket_1 = 193, + eq_ana_bndy_bucket_2 = 194, + eq_ana_bndy_bucket_3 = 195, + eq_ana_bndy_bucket_4 = 196, + eq_ana_bndy_bucket_5 = 197, + eq_ana_bndy_bucket_6 = 198, + eq_ana_bndy_bucket_7 = 199, + eq_ana_bndy_bucket_8 = 200, + eq_ana_bndy_bucket_9 = 201, + eq_ana_bndy_bucket_10 = 202, + eq_ana_bndy_bucket_11 = 203, + eq_ana_bndy_bucket_12 = 204, + eq_ana_bndy_bucket_13 = 205, + eq_ana_bndy_bucket_14 = 206, + eq_ana_bndy_bucket_15 = 207, + eq_ana_bndy_bucket_16 = 208, + eq_ana_bndy_bucket_17 = 209, + eq_ana_bndy_bucket_18 = 210, + eq_ana_bndy_bucket_19 = 211, + eq_ana_bndy_bucket_20 = 212, + eq_ana_bndy_bucket_21 = 213, + eq_ana_bndy_bucket_22 = 214, + eq_ana_bndy_bucket_23 = 215, + eq_ana_bndy_bucket_24 = 216, + eq_ana_bndy_bucket_25 = 217, + eq_ana_bndy_l3dcc_bucket_26 = 218, + eq_ana_mode = 219, // Quad Chiplet Rings // EQ0 - EQ5 instance specific Rings - eq_repr = 245, - ex_l3_repr = 246, - ex_l2_repr = 247, - ex_l3_refr_repr = 248, + eq_repr = 220, + ex_l3_repr = 221, + ex_l2_repr = 222, + ex_l3_refr_repr = 223, // Core Chiplet Rings // Common - apply to all Core instances - ec_func = 249, - ec_gptr = 250, - ec_time = 251, - ec_mode = 252, + ec_func = 224, + ec_gptr = 225, + ec_time = 226, + ec_mode = 227, // Core Chiplet Rings // EC0 - EC23 instance specific Ring - ec_repr = 253, + ec_repr = 228, //*************************** // Rings needed for SBE - End //*************************** @@ -613,16 +584,7 @@ enum RingOffset xb_io2_time = 11, xb_pll_gptr = 12, xb_pll_bndy = 13, - // The values for this and the following constant are purposefully made - // identical. The idea is to enable the user to specify directly the bucket - // number or use the Attribute. Giving same number here will enable - // evaluating to the same offset. - xb_pll_bndy_bucket_1 = 13, - xb_pll_bndy_bucket_2 = 14, - xb_pll_bndy_bucket_3 = 15, - xb_pll_bndy_bucket_4 = 16, - xb_pll_bndy_bucket_5 = 17, - xb_pll_func = 18, + xb_pll_func = 14, // Instance Rings xb_repr = (0 | INSTANCE_RING_MARK), xb_io0_repr = (1 | INSTANCE_RING_MARK), @@ -633,7 +595,7 @@ enum RingOffset static const CHIPLET_DATA g_xbData = { 6, // X-Bus Chiplet ID is 6 - 19, // 19 common rings for X-Bus Chiplet + 15, // 15 common rings for X-Bus Chiplet 4 // 4 instance specific rings for XB chiplet }; }; // end of namespace XB @@ -659,7 +621,6 @@ enum RingOffset mc_iom23_gptr = 7, mc_iom23_time = 8, mc_pll_gptr = 9, - // To find the bucket id for MC PLL, NEST_PLL_BUCKET attribute will be used mc_pll_bndy = 10, mc_pll_bndy_bucket_1 = 10, mc_pll_bndy_bucket_2 = 11, @@ -697,16 +658,7 @@ enum RingOffset ob0_time = 2, ob0_pll_gptr = 3, ob0_pll_bndy = 4, - // The values for this and the following constant are purposefully made - // identical. The idea is to enable the user to specify directly the bucket - // number or use the Attribute. Giving same number here will enable - // evaluating to the same offset. - ob0_pll_bndy_bucket_1 = 4, - ob0_pll_bndy_bucket_2 = 5, - ob0_pll_bndy_bucket_3 = 6, - ob0_pll_bndy_bucket_4 = 7, - ob0_pll_bndy_bucket_5 = 8, - ob0_pll_func = 9, + ob0_pll_func = 5, // Instance Rings ob0_repr = (0 | INSTANCE_RING_MARK) }; @@ -714,7 +666,7 @@ enum RingOffset static const CHIPLET_DATA g_ob0Data = { 9, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 10, // 10 common rings for OB Chiplet + 6, // 6 common rings for OB Chiplet 1 // 1 instance specific rings for each OB chiplet }; }; // end of namespace OB0 @@ -735,16 +687,7 @@ enum RingOffset ob1_time = 2, ob1_pll_gptr = 3, ob1_pll_bndy = 4, - // The values for this and the following constant are purposefully made - // identical. The idea is to enable the user to specify directly the bucket - // number or use the Attribute. Giving same number here will enable - // evaluating to the same offset. - ob1_pll_bndy_bucket_1 = 4, - ob1_pll_bndy_bucket_2 = 5, - ob1_pll_bndy_bucket_3 = 6, - ob1_pll_bndy_bucket_4 = 7, - ob1_pll_bndy_bucket_5 = 8, - ob1_pll_func = 9, + ob1_pll_func = 5, // Instance Rings ob1_repr = (0 | INSTANCE_RING_MARK) }; @@ -752,8 +695,8 @@ enum RingOffset static const CHIPLET_DATA g_ob1Data = { 10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 10, // 10 common rings for OB Chiplet - 1 // 1 instance specific rings for each OB chiplet + 6, // 6 common rings for OB Chiplet + 1 // 1 instance specific rings for each OB chiplet }; }; // end of namespace OB1 @@ -774,16 +717,7 @@ enum RingOffset ob2_time = 2, ob2_pll_gptr = 3, ob2_pll_bndy = 4, - // The values for this and the following constant are purposefully made - // identical. The idea is to enable the user to specify directly the bucket - // number or use the Attribute. Giving same number here will enable - // evaluating to the same offset. - ob2_pll_bndy_bucket_1 = 4, - ob2_pll_bndy_bucket_2 = 5, - ob2_pll_bndy_bucket_3 = 6, - ob2_pll_bndy_bucket_4 = 7, - ob2_pll_bndy_bucket_5 = 8, - ob2_pll_func = 9, + ob2_pll_func = 5, // Instance Rings ob2_repr = (0 | INSTANCE_RING_MARK) }; @@ -791,8 +725,8 @@ enum RingOffset static const CHIPLET_DATA g_ob2Data = { 11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 10, // 10 common rings for OB Chiplet - 1 // 1 instance specific rings for each OB chiplet + 6, // 6 common rings for OB Chiplet + 1 // 1 instance specific rings for each OB chiplet }; }; // end of namespace OB2 @@ -812,16 +746,7 @@ enum RingOffset ob3_time = 2, ob3_pll_gptr = 3, ob3_pll_bndy = 4, - // The values for this and the following constant are purposefully made - // identical. The idea is to enable the user to specify directly the bucket - // number or use the Attribute. Giving same number here will enable - // evaluating to the same offset. - ob3_pll_bndy_bucket_1 = 4, - ob3_pll_bndy_bucket_2 = 5, - ob3_pll_bndy_bucket_3 = 6, - ob3_pll_bndy_bucket_4 = 7, - ob3_pll_bndy_bucket_5 = 8, - ob3_pll_func = 9, + ob3_pll_func = 5, // Instance Rings ob3_repr = (0 | INSTANCE_RING_MARK) }; @@ -829,8 +754,8 @@ enum RingOffset static const CHIPLET_DATA g_ob3Data = { 12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 10, // 10 common rings for OB Chiplet - 1 // 1 instance specific rings for each OB chiplet + 6, // 10 common rings for OB Chiplet + 1 // 1 instance specific rings for each OB chiplet }; }; // end of namespace OB2 namespace PCI0 @@ -847,7 +772,7 @@ enum RingOffset pci0_fure = 0, pci0_gptr = 1, pci0_time = 2, - pci0_pll_func = 3, + pci0_pll_bndy = 3, pci0_pll_gptr = 4, // Instance Rings pci0_repr = (0 | INSTANCE_RING_MARK) @@ -875,7 +800,7 @@ enum RingOffset pci1_fure = 0, pci1_gptr = 1, pci1_time = 2, - pci1_pll_func = 3, + pci1_pll_bndy = 3, pci1_pll_gptr = 4, // Instance Rings pci1_repr = (0 | INSTANCE_RING_MARK) @@ -903,7 +828,7 @@ enum RingOffset pci2_fure = 0, pci2_gptr = 1, pci2_time = 2, - pci2_pll_func = 3, + pci2_pll_bndy = 3, pci2_pll_gptr = 4, // Instance Rings pci2_repr = (0 | INSTANCE_RING_MARK) @@ -1044,574 +969,470 @@ struct ringProperties_t #ifndef __PPE__ static const ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] = { - // Pervasive Ring - {PERV::perv_fure, "perv_fure"}, // 0 - {PERV::perv_gptr, "perv_gptr"}, // 1 - {PERV::perv_time, "perv_time"}, // 2 - {PERV::occ_fure, "occ_fure"}, // 3 - {PERV::occ_gptr, "occ_gptr"}, // 4 - {PERV::occ_time, "occ_time"}, // 5 - {PERV::perv_ana_func, "perv_ana_func"}, // 6 - {PERV::perv_ana_gptr, "perv_ana_gptr"}, // 7 - {PERV::perv_pll_gptr, "perv_pll_gptr"}, // 8 - {PERV::perv_pll_bndy, "perv_pll_bndy"}, // 9 - {PERV::perv_pll_bndy_bucket_1, "perv_pll_bndy_bucket_1"}, // 10 - {PERV::perv_pll_bndy_bucket_2, "perv_pll_bndy_bucket_2"}, // 11 - {PERV::perv_pll_bndy_bucket_3, "perv_pll_bndy_bucket_3"}, // 12 - {PERV::perv_pll_bndy_bucket_4, "perv_pll_bndy_bucket_4"}, // 13 - {PERV::perv_pll_bndy_bucket_5, "perv_pll_bndy_bucket_5"}, // 14 - {PERV::perv_pll_func, "perv_pll_func"}, // 15 - {PERV::perv_pibnet_gptr, "perv_pibnet_gptr"}, // 16 - {PERV::perv_pibnet_time, "perv_pibnet_time"}, // 17 - {PERV::perv_repr, "perv_repr"}, // 18 - {PERV::occ_repr, "occ_repr"}, // 19 - {PERV::perv_pibnet_repr, "perv_pibnet_repr"}, // 20 - - // Nest N0 Ring - {N0::n0_fure, "n0_fure"}, // 21 - {N0::n0_gptr, "n0_gptr"}, // 22 - {N0::n0_time, "n0_time"}, // 23 - {N0::n0_nx_fure, "n0_nx_fure"}, // 24 - {N0::n0_nx_gptr, "n0_nx_gptr"}, // 25 - {N0::n0_nx_time, "n0_nx_time"}, // 26 - {N0::n0_cxa0_fure, "n0_cxa0_fure"}, // 27 - {N0::n0_cxa0_gptr, "n0_cxa0_gptr"}, // 28 - {N0::n0_cxa0_time, "n0_cxa0_time"}, // 29 - {N0::n0_repr, "n0_repr"}, // 30 - {N0::n0_nx_repr, "n0_nx_repr"}, // 31 - {N0::n0_cxa0_repr, "n0_cxa0_repr"}, // 32 - - // Nest N1 Ring - {N1::n1_fure, "n1_fure"}, // 33 - {N1::n1_gptr, "n1_gptr"}, // 34 - {N1::n1_time, "n1_time"}, // 35 - {N1::n1_ioo0_fure, "n1_ioo0_fure"}, // 36 - {N1::n1_ioo0_gptr, "n1_ioo0_gptr"}, // 37 - {N1::n1_ioo0_time, "n1_ioo0_time"}, // 38 - {N1::n1_ioo1_fure, "n1_ioo1_fure"}, // 39 - {N1::n1_ioo1_gptr, "n1_ioo1_gptr"}, // 40 - {N1::n1_ioo1_time, "n1_ioo1_time"}, // 41 - {N1::n1_mcs23_fure, "n1_mcs23_fure"}, // 42 - {N1::n1_mcs23_gptr, "n1_mcs23_gptr"}, // 43 - {N1::n1_mcs23_time, "n1_mcs23_time"}, // 44 - {N1::n1_repr, "n1_repr"}, // 45 - {N1::n1_ioo0_repr, "n1_ioo0_repr"}, // 46 - {N1::n1_ioo1_repr, "n1_ioo1_repr"}, // 47 - {N1::n1_mcs23_repr, "n1_mcs23_repr"}, // 48 - - // Nest N2 Ring - {N2::n2_fure, "n2_fure"}, // 49 - {N2::n2_gptr, "n2_gptr"}, // 50 - {N2::n2_time, "n2_time"}, // 51 - {N2::n2_cxa1_fure, "n2_cxa1_fure"}, // 52 - {N2::n2_cxa1_gptr, "n2_cxa1_gptr"}, // 53 - {N2::n2_cxa1_time, "n2_cxa1_time"}, // 54 - {N2::n2_psi_fure, "n2_psi_fure"}, // 55 - {N2::n2_psi_gptr, "n2_psi_gptr"}, // 56 - {N2::n2_psi_time, "n2_psi_time"}, // 57 - {N2::n2_repr, "n2_repr"}, // 58 - {N2::n2_cxa1_repr, "n2_cxa1_repr"}, // 59 - {N2::n2_psi_repr, "n2_psi_repr"}, // 60 - {INVALID_RING, ""}, // 61 // for future. - - // Nest N3 Ring - {N3::n3_fure, "n3_fure"}, // 62 - {N3::n3_gptr, "n3_gptr"}, // 63 - {N3::n3_time, "n3_time"}, // 64 - {N3::n3_mcs01_fure, "n3_mcs01_fure"}, // 65 - {N3::n3_mcs01_gptr, "n3_mcs01_gptr"}, // 66 - {N3::n3_mcs01_time, "n3_mcs01_time"}, // 67 - {N3::n3_np_fure, "n3_np_fure"}, // 68 - {N3::n3_np_gptr, "n3_np_gptr"}, // 69 - {N3::n3_np_time, "n3_np_time"}, // 70 - {N3::n3_repr, "n3_repr"}, // 71 - {N3::n3_mcs01_repr, "n3_mcs01_repr"}, // 72 - {N3::n3_np_repr, "n3_np_repr"}, // 73 - {INVALID_RING, ""}, // 74 // for future. - - // XB Ring - {XB::xb_fure, "xb_fure"}, // 75 - {XB::xb_gptr, "xb_gptr"}, // 76 - {XB::xb_time, "xb_time"}, // 77 - {XB::xb_io0_fure, "xb_io0_fure"}, // 78 - {XB::xb_io0_gptr, "xb_io0_gptr"}, // 79 - {XB::xb_io0_time, "xb_io0_time"}, // 80 - {XB::xb_io1_fure, "xb_io1_fure"}, // 81 - {XB::xb_io1_gptr, "xb_io1_gptr"}, // 82 - {XB::xb_io1_time, "xb_io1_time"}, // 83 - {XB::xb_io2_fure, "xb_io2_fure"}, // 84 - {XB::xb_io2_gptr, "xb_io2_gptr"}, // 85 - {XB::xb_io2_time, "xb_io2_time"}, // 86 - {XB::xb_pll_gptr, "xb_pll_gptr"}, // 87 - {XB::xb_pll_bndy, "xb_pll_bndy"}, // 88 - {XB::xb_pll_bndy_bucket_1, "xb_pll_bndy_bucket_1"}, // 89 - {XB::xb_pll_bndy_bucket_2, "xb_pll_bndy_bucket_2"}, // 90 - {XB::xb_pll_bndy_bucket_3, "xb_pll_bndy_bucket_3"}, // 91 - {XB::xb_pll_bndy_bucket_4, "xb_pll_bndy_bucket_4"}, // 92 - {XB::xb_pll_bndy_bucket_5, "xb_pll_bndy_bucket_5"}, // 93 - {XB::xb_pll_func, "xb_pll_func"}, // 94 - {XB::xb_repr, "xb_repr"}, // 95 - {XB::xb_io0_repr, "xb_io0_repr"}, // 96 - {XB::xb_io1_repr, "xb_io1_repr"}, // 97 - {XB::xb_io2_repr, "xb_io2_repr"}, // 98 - {INVALID_RING, ""}, // 99 // for future. - {INVALID_RING, ""}, // 100 // for future. - - // MC Ring - {MC::mc_fure, "mc_fure"}, // 101 - {MC::mc_gptr, "mc_gptr"}, // 102 - {MC::mc_time, "mc_time"}, // 103 - {MC::mc_iom01_fure, "mc_iom01_fure"}, // 104 - {MC::mc_iom01_gptr, "mc_iom01_gptr"}, // 105 - {MC::mc_iom01_time, "mc_iom01_time"}, // 106 - {MC::mc_iom23_fure, "mc_iom23_fure"}, // 107 - {MC::mc_iom23_gptr, "mc_iom23_gptr"}, // 108 - {MC::mc_iom23_time, "mc_iom23_time"}, // 109 - {MC::mc_pll_gptr, "mc_pll_gptr"}, // 110 - {MC::mc_pll_bndy, "mc_pll_bndy"}, // 111 - {MC::mc_pll_bndy_bucket_1, "mc_pll_bndy_bucket_1"}, // 112 - {MC::mc_pll_bndy_bucket_2, "mc_pll_bndy_bucket_2"}, // 113 - {MC::mc_pll_bndy_bucket_3, "mc_pll_bndy_bucket_3"}, // 114 - {MC::mc_pll_bndy_bucket_4, "mc_pll_bndy_bucket_4"}, // 115 - {MC::mc_pll_bndy_bucket_5, "mc_pll_bndy_bucket_5"}, // 116 - {MC::mc_pll_func, "mc_pll_func"}, // 117 - {MC::mc_repr, "mc_repr"}, // 118 - {MC::mc_iom01_repr, "mc_iom01_repr"}, // 119 - {MC::mc_iom23_repr, "mc_iom23_repr"}, // 120 - {INVALID_RING, ""}, // 121 // for future. - {INVALID_RING, ""}, // 122 // for future. - - // OB Ring - {OB0::ob0_fure, "ob0_fure"}, // 123 - {OB0::ob0_gptr, "ob0_gptr"}, // 124 - {OB0::ob0_time, "ob0_time"}, // 125 - {OB0::ob0_pll_gptr, "ob0_pll_gptr"}, // 126 - {OB0::ob0_pll_bndy, "ob0_pll_bndy"}, // 127 - {OB0::ob0_pll_bndy_bucket_1, "ob0_pll_bndy_bucket_1"}, // 128 - {OB0::ob0_pll_bndy_bucket_2, "ob0_pll_bndy_bucket_2"}, // 129 - {OB0::ob0_pll_bndy_bucket_3, "ob0_pll_bndy_bucket_3"}, // 130 - {OB0::ob0_pll_bndy_bucket_4, "ob0_pll_bndy_bucket_4"}, // 131 - {OB0::ob0_pll_bndy_bucket_5, "ob0_pll_bndy_bucket_5"}, // 132 - {OB0::ob0_pll_func, "ob0_pll_func"}, // 133 - {OB0::ob0_repr, "ob0_repr"}, // 134 - {INVALID_RING, ""}, // 135 // for future. - {INVALID_RING, ""}, // 136 // for future. - - {OB1::ob1_fure, "ob1_fure"}, // 137 - {OB1::ob1_gptr, "ob1_gptr"}, // 138 - {OB1::ob1_time, "ob1_time"}, // 139 - {OB1::ob1_pll_gptr, "ob1_pll_gptr"}, // 140 - {OB1::ob1_pll_bndy, "ob1_pll_bndy"}, // 141 - {OB1::ob1_pll_bndy_bucket_1, "ob1_pll_bndy_bucket_1"}, // 142 - {OB1::ob1_pll_bndy_bucket_2, "ob1_pll_bndy_bucket_2"}, // 143 - {OB1::ob1_pll_bndy_bucket_3, "ob1_pll_bndy_bucket_3"}, // 144 - {OB1::ob1_pll_bndy_bucket_4, "ob1_pll_bndy_bucket_4"}, // 145 - {OB1::ob1_pll_bndy_bucket_5, "ob1_pll_bndy_bucket_5"}, // 146 - {OB1::ob1_pll_func, "ob1_pll_func"}, // 147 - {OB1::ob1_repr, "ob1_repr"}, // 148 - {INVALID_RING, ""}, // 149 // for future. - {INVALID_RING, ""}, // 150 // for future. - - {OB2::ob2_fure, "ob2_fure"}, // 151 - {OB2::ob2_gptr, "ob2_gptr"}, // 152 - {OB2::ob2_time, "ob2_time"}, // 153 - {OB2::ob2_pll_gptr, "ob2_pll_gptr"}, // 154 - {OB2::ob2_pll_bndy, "ob2_pll_bndy"}, // 155 - {OB2::ob2_pll_bndy_bucket_1, "ob2_pll_bndy_bucket_1"}, // 156 - {OB2::ob2_pll_bndy_bucket_2, "ob2_pll_bndy_bucket_2"}, // 157 - {OB2::ob2_pll_bndy_bucket_3, "ob2_pll_bndy_bucket_3"}, // 158 - {OB2::ob2_pll_bndy_bucket_4, "ob2_pll_bndy_bucket_4"}, // 159 - {OB2::ob2_pll_bndy_bucket_5, "ob2_pll_bndy_bucket_5"}, // 160 - {OB2::ob2_pll_func, "ob2_pll_func"}, // 161 - {OB2::ob2_repr, "ob2_repr"}, // 162 - {INVALID_RING, ""}, // 163 // for future. - {INVALID_RING, ""}, // 164 // for future. - - {OB3::ob3_fure, "ob3_fure"}, // 165 - {OB3::ob3_gptr, "ob3_gptr"}, // 166 - {OB3::ob3_time, "ob3_time"}, // 167 - {OB3::ob3_pll_gptr, "ob3_pll_gptr"}, // 168 - {OB3::ob3_pll_bndy, "ob3_pll_bndy"}, // 169 - {OB3::ob3_pll_bndy_bucket_1, "ob3_pll_bndy_bucket_1"}, // 170 - {OB3::ob3_pll_bndy_bucket_2, "ob3_pll_bndy_bucket_2"}, // 171 - {OB3::ob3_pll_bndy_bucket_3, "ob3_pll_bndy_bucket_3"}, // 172 - {OB3::ob3_pll_bndy_bucket_4, "ob3_pll_bndy_bucket_4"}, // 173 - {OB3::ob3_pll_bndy_bucket_5, "ob3_pll_bndy_bucket_5"}, // 174 - {OB3::ob3_pll_func, "ob3_pll_func"}, // 175 - {OB3::ob3_repr, "ob3_repr"}, // 176 - {INVALID_RING, ""}, // 177 // for future. - {INVALID_RING, ""}, // 178 // for future. - - // PCI0 Ring - {PCI0::pci0_fure, "pci0_fure"}, // 179 - {PCI0::pci0_gptr, "pci0_gptr"}, // 180 - {PCI0::pci0_time, "pci0_time"}, // 181 - {PCI0::pci0_pll_func, "pci0_pll_func"}, // 182 - {PCI0::pci0_pll_gptr, "pci0_pll_gptr"}, // 183 - {PCI0::pci0_repr, "pci0_repr"}, // 184 - // PCI1 Ring - {PCI1::pci1_fure, "pci1_fure"}, // 185 - {PCI1::pci1_gptr, "pci1_gptr"}, // 186 - {PCI1::pci1_time, "pci1_time"}, // 187 - {PCI1::pci1_pll_func, "pci1_pll_func"}, // 188 - {PCI1::pci1_pll_gptr, "pci1_pll_gptr"}, // 189 - {PCI1::pci1_repr, "pci1_repr"}, // 190 - // PCI2 Ring - {PCI2::pci2_fure, "pci2_fure"}, // 191 - {PCI2::pci2_gptr, "pci2_gptr"}, // 192 - {PCI2::pci2_time, "pci2_time"}, // 193 - {PCI2::pci2_pll_func, "pci2_pll_func"}, // 194 - {PCI2::pci2_pll_gptr, "pci2_pll_gptr"}, // 195 - {PCI2::pci2_repr, "pci2_repr"}, // 196 - - // EQ Ring - {EQ::eq_fure, "eq_fure"}, // 197 - {EQ::eq_gptr, "eq_gptr"}, // 198 - {EQ::eq_time, "eq_time"}, // 199 - {EQ::eq_mode, "eq_mode"}, // 200 - {EQ::ex_l3_fure, "ex_l3_fure"}, // 201 - {EQ::ex_l3_gptr, "ex_l3_gptr"}, // 202 - {EQ::ex_l3_time, "ex_l3_time"}, // 203 - {EQ::ex_l2_mode, "ex_l2_mode"}, // 204 - {EQ::ex_l2_fure, "ex_l2_fure"}, // 205 - {EQ::ex_l2_gptr, "ex_l2_gptr"}, // 206 - {EQ::ex_l2_time, "ex_l2_time"}, // 207 - {EQ::ex_l3_refr_fure, "ex_l3_refr_fure"}, // 208 - {EQ::ex_l3_refr_gptr, "ex_l3_refr_gptr"}, // 209 - {EQ::ex_l3_refr_time, "ex_l3_refr_time"}, // 210 - {EQ::eq_ana_func, "eq_ana_func"}, // 211 - {EQ::eq_ana_gptr, "eq_ana_gptr"}, // 212 - {EQ::eq_dpll_func, "eq_dpll_func"}, // 213 - {EQ::eq_dpll_gptr, "eq_dpll_gptr"}, // 214 - {EQ::eq_dpll_mode, "eq_dpll_mode"}, // 215 - {EQ::eq_ana_bndy, "eq_ana_bndy"}, // 216 - {EQ::eq_ana_bndy_bucket_0, "eq_ana_bndy_bucket_0"}, // 217 - {EQ::eq_ana_bndy_bucket_1, "eq_ana_bndy_bucket_1"}, // 218 - {EQ::eq_ana_bndy_bucket_2, "eq_ana_bndy_bucket_2"}, // 219 - {EQ::eq_ana_bndy_bucket_3, "eq_ana_bndy_bucket_3"}, // 220 - {EQ::eq_ana_bndy_bucket_4, "eq_ana_bndy_bucket_4"}, // 221 - {EQ::eq_ana_bndy_bucket_5, "eq_ana_bndy_bucket_5"}, // 222 - {EQ::eq_ana_bndy_bucket_6, "eq_ana_bndy_bucket_6"}, // 223 - {EQ::eq_ana_bndy_bucket_7, "eq_ana_bndy_bucket_7"}, // 224 - {EQ::eq_ana_bndy_bucket_8, "eq_ana_bndy_bucket_8"}, // 225 - {EQ::eq_ana_bndy_bucket_9, "eq_ana_bndy_bucket_9"}, // 226 - {EQ::eq_ana_bndy_bucket_10, "eq_ana_bndy_bucket_10"}, // 227 - {EQ::eq_ana_bndy_bucket_11, "eq_ana_bndy_bucket_11"}, // 228 - {EQ::eq_ana_bndy_bucket_12, "eq_ana_bndy_bucket_12"}, // 229 - {EQ::eq_ana_bndy_bucket_13, "eq_ana_bndy_bucket_13"}, // 230 - {EQ::eq_ana_bndy_bucket_14, "eq_ana_bndy_bucket_14"}, // 231 - {EQ::eq_ana_bndy_bucket_15, "eq_ana_bndy_bucket_15"}, // 232 - {EQ::eq_ana_bndy_bucket_16, "eq_ana_bndy_bucket_16"}, // 233 - {EQ::eq_ana_bndy_bucket_17, "eq_ana_bndy_bucket_17"}, // 234 - {EQ::eq_ana_bndy_bucket_18, "eq_ana_bndy_bucket_18"}, // 235 - {EQ::eq_ana_bndy_bucket_19, "eq_ana_bndy_bucket_19"}, // 236 - {EQ::eq_ana_bndy_bucket_20, "eq_ana_bndy_bucket_20"}, // 237 - {EQ::eq_ana_bndy_bucket_21, "eq_ana_bndy_bucket_21"}, // 238 - {EQ::eq_ana_bndy_bucket_22, "eq_ana_bndy_bucket_22"}, // 239 - {EQ::eq_ana_bndy_bucket_23, "eq_ana_bndy_bucket_23"}, // 240 - {EQ::eq_ana_bndy_bucket_24, "eq_ana_bndy_bucket_24"}, // 241 - {EQ::eq_ana_bndy_bucket_25, "eq_ana_bndy_bucket_25"}, // 242 - {EQ::eq_ana_bndy_l3dcc_bucket_26, "eq_ana_bndy_bucket_26"}, // 243 - {EQ::eq_ana_mode, "eq_ana_mode"}, // 244 - {EQ::eq_repr, "eq_repr"}, // 245 - {EQ::ex_l3_repr, "ex_l3_repr"}, // 246 - {EQ::ex_l2_repr, "ex_l2_repr"}, // 247 - {EQ::ex_l3_refr_repr, "ex_l3_refr_repr"}, // 248 - - // Core Ring - {EC::ec_func, "ec_func"}, // 249 - {EC::ec_gptr, "ec_gptr"}, // 250 - {EC::ec_time, "ec_time"}, // 251 - {EC::ec_mode, "ec_mode"}, // 252 - {EC::ec_repr, "ec_repr"} // 253 + { PERV::perv_fure , "perv_fure" , PERV_TYPE }, // 0 + { PERV::perv_gptr , "perv_gptr" , PERV_TYPE }, // 1 + { PERV::perv_time , "perv_time" , PERV_TYPE }, // 2 + { PERV::occ_fure , "occ_fure" , PERV_TYPE }, // 3 + { PERV::occ_gptr , "occ_gptr" , PERV_TYPE }, // 4 + { PERV::occ_time , "occ_time" , PERV_TYPE }, // 5 + { PERV::perv_ana_func , "perv_ana_func" , PERV_TYPE }, // 6 + { PERV::perv_ana_gptr , "perv_ana_gptr" , PERV_TYPE }, // 7 + { PERV::perv_pll_gptr , "perv_pll_gptr" , PERV_TYPE }, // 8 + { PERV::perv_pll_bndy , "perv_pll_bndy" , PERV_TYPE }, // 9 + { PERV::perv_pll_bndy_bucket_1 , "perv_pll_bndy_bucket_1" , PERV_TYPE }, // 10 + { PERV::perv_pll_bndy_bucket_2 , "perv_pll_bndy_bucket_2" , PERV_TYPE }, // 11 + { PERV::perv_pll_bndy_bucket_3 , "perv_pll_bndy_bucket_3" , PERV_TYPE }, // 12 + { PERV::perv_pll_bndy_bucket_4 , "perv_pll_bndy_bucket_4" , PERV_TYPE }, // 13 + { PERV::perv_pll_bndy_bucket_5 , "perv_pll_bndy_bucket_5" , PERV_TYPE }, // 14 + { PERV::perv_pll_func , "perv_pll_func" , PERV_TYPE }, // 15 + { PERV::perv_pibnet_gptr , "perv_pibnet_gptr" , PERV_TYPE }, // 16 + { PERV::perv_pibnet_time , "perv_pibnet_time" , PERV_TYPE }, // 17 + { PERV::perv_repr , "perv_repr" , PERV_TYPE }, // 18 + { PERV::occ_repr , "occ_repr" , PERV_TYPE }, // 19 + { PERV::perv_pibnet_repr , "perv_pibnet_repr" , PERV_TYPE }, // 20 + { N0::n0_fure , "n0_fure" , N0_TYPE }, // 21 + { N0::n0_gptr , "n0_gptr" , N0_TYPE }, // 22 + { N0::n0_time , "n0_time" , N0_TYPE }, // 23 + { N0::n0_nx_fure , "n0_nx_fure" , N0_TYPE }, // 24 + { N0::n0_nx_gptr , "n0_nx_gptr" , N0_TYPE }, // 25 + { N0::n0_nx_time , "n0_nx_time" , N0_TYPE }, // 26 + { N0::n0_cxa0_fure , "n0_cxa0_fure" , N0_TYPE }, // 27 + { N0::n0_cxa0_gptr , "n0_cxa0_gptr" , N0_TYPE }, // 28 + { N0::n0_cxa0_time , "n0_cxa0_time" , N0_TYPE }, // 29 + { N0::n0_repr , "n0_repr" , N0_TYPE }, // 30 + { N0::n0_nx_repr , "n0_nx_repr" , N0_TYPE }, // 31 + { N0::n0_cxa0_repr , "n0_cxa0_repr" , N0_TYPE }, // 32 + { N1::n1_fure , "n1_fure" , N1_TYPE }, // 33 + { N1::n1_gptr , "n1_gptr" , N1_TYPE }, // 34 + { N1::n1_time , "n1_time" , N1_TYPE }, // 35 + { N1::n1_ioo0_fure , "n1_ioo0_fure" , N1_TYPE }, // 36 + { N1::n1_ioo0_gptr , "n1_ioo0_gptr" , N1_TYPE }, // 37 + { N1::n1_ioo0_time , "n1_ioo0_time" , N1_TYPE }, // 38 + { N1::n1_ioo1_fure , "n1_ioo1_fure" , N1_TYPE }, // 39 + { N1::n1_ioo1_gptr , "n1_ioo1_gptr" , N1_TYPE }, // 40 + { N1::n1_ioo1_time , "n1_ioo1_time" , N1_TYPE }, // 41 + { N1::n1_mcs23_fure , "n1_mcs23_fure" , N1_TYPE }, // 42 + { N1::n1_mcs23_gptr , "n1_mcs23_gptr" , N1_TYPE }, // 43 + { N1::n1_mcs23_time , "n1_mcs23_time" , N1_TYPE }, // 44 + { N1::n1_repr , "n1_repr" , N1_TYPE }, // 45 + { N1::n1_ioo0_repr , "n1_ioo0_repr" , N1_TYPE }, // 46 + { N1::n1_ioo1_repr , "n1_ioo1_repr" , N1_TYPE }, // 47 + { N1::n1_mcs23_repr , "n1_mcs23_repr" , N1_TYPE }, // 48 + { N2::n2_fure , "n2_fure" , N2_TYPE }, // 49 + { N2::n2_gptr , "n2_gptr" , N2_TYPE }, // 50 + { N2::n2_time , "n2_time" , N2_TYPE }, // 51 + { N2::n2_cxa1_fure , "n2_cxa1_fure" , N2_TYPE }, // 52 + { N2::n2_cxa1_gptr , "n2_cxa1_gptr" , N2_TYPE }, // 53 + { N2::n2_cxa1_time , "n2_cxa1_time" , N2_TYPE }, // 54 + { N2::n2_psi_fure , "n2_psi_fure" , N2_TYPE }, // 55 + { N2::n2_psi_gptr , "n2_psi_gptr" , N2_TYPE }, // 56 + { N2::n2_psi_time , "n2_psi_time" , N2_TYPE }, // 57 + { N2::n2_repr , "n2_repr" , N2_TYPE }, // 58 + { N2::n2_cxa1_repr , "n2_cxa1_repr" , N2_TYPE }, // 59 + { N2::n2_psi_repr , "n2_psi_repr" , N2_TYPE }, // 60 + { INVALID_RING , "invalid" , N2_TYPE }, // 61 + { N3::n3_fure , "n3_fure" , N3_TYPE }, // 62 + { N3::n3_gptr , "n3_gptr" , N3_TYPE }, // 63 + { N3::n3_time , "n3_time" , N3_TYPE }, // 64 + { N3::n3_mcs01_fure , "n3_mcs01_fure" , N3_TYPE }, // 65 + { N3::n3_mcs01_gptr , "n3_mcs01_gptr" , N3_TYPE }, // 66 + { N3::n3_mcs01_time , "n3_mcs01_time" , N3_TYPE }, // 67 + { N3::n3_np_fure , "n3_np_fure" , N3_TYPE }, // 68 + { N3::n3_np_gptr , "n3_np_gptr" , N3_TYPE }, // 69 + { N3::n3_np_time , "n3_np_time" , N3_TYPE }, // 70 + { N3::n3_repr , "n3_repr" , N3_TYPE }, // 71 + { N3::n3_mcs01_repr , "n3_mcs01_repr" , N3_TYPE }, // 72 + { N3::n3_np_repr , "n3_np_repr" , N3_TYPE }, // 73 + { INVALID_RING , "invalid" , N3_TYPE }, // 74 + { XB::xb_fure , "xb_fure" , XB_TYPE }, // 75 + { XB::xb_gptr , "xb_gptr" , XB_TYPE }, // 76 + { XB::xb_time , "xb_time" , XB_TYPE }, // 77 + { XB::xb_io0_fure , "xb_io0_fure" , XB_TYPE }, // 78 + { XB::xb_io0_gptr , "xb_io0_gptr" , XB_TYPE }, // 79 + { XB::xb_io0_time , "xb_io0_time" , XB_TYPE }, // 80 + { XB::xb_io1_fure , "xb_io1_fure" , XB_TYPE }, // 81 + { XB::xb_io1_gptr , "xb_io1_gptr" , XB_TYPE }, // 82 + { XB::xb_io1_time , "xb_io1_time" , XB_TYPE }, // 83 + { XB::xb_io2_fure , "xb_io2_fure" , XB_TYPE }, // 84 + { XB::xb_io2_gptr , "xb_io2_gptr" , XB_TYPE }, // 85 + { XB::xb_io2_time , "xb_io2_time" , XB_TYPE }, // 86 + { XB::xb_pll_gptr , "xb_pll_gptr" , XB_TYPE }, // 87 + { XB::xb_pll_bndy , "xb_pll_bndy" , XB_TYPE }, // 88 + { XB::xb_pll_func , "xb_pll_func" , XB_TYPE }, // 89 + { XB::xb_repr , "xb_repr" , XB_TYPE }, // 90 + { XB::xb_io0_repr , "xb_io0_repr" , XB_TYPE }, // 91 + { XB::xb_io1_repr , "xb_io1_repr" , XB_TYPE }, // 92 + { XB::xb_io2_repr , "xb_io2_repr" , XB_TYPE }, // 93 + { INVALID_RING , "invalid" , XB_TYPE }, // 94 + { INVALID_RING , "invalid" , XB_TYPE }, // 95 + { MC::mc_fure , "mc_fure" , MC_TYPE }, // 96 + { MC::mc_gptr , "mc_gptr" , MC_TYPE }, // 97 + { MC::mc_time , "mc_time" , MC_TYPE }, // 98 + { MC::mc_iom01_fure , "mc_iom01_fure" , MC_TYPE }, // 99 + { MC::mc_iom01_gptr , "mc_iom01_gptr" , MC_TYPE }, // 100 + { MC::mc_iom01_time , "mc_iom01_time" , MC_TYPE }, // 101 + { MC::mc_iom23_fure , "mc_iom23_fure" , MC_TYPE }, // 102 + { MC::mc_iom23_gptr , "mc_iom23_gptr" , MC_TYPE }, // 103 + { MC::mc_iom23_time , "mc_iom23_time" , MC_TYPE }, // 104 + { MC::mc_pll_gptr , "mc_pll_gptr" , MC_TYPE }, // 105 + { MC::mc_pll_bndy , "mc_pll_bndy" , MC_TYPE }, // 106 + { MC::mc_pll_bndy_bucket_1 , "mc_pll_bndy_bucket_1" , MC_TYPE }, // 107 + { MC::mc_pll_bndy_bucket_2 , "mc_pll_bndy_bucket_2" , MC_TYPE }, // 108 + { MC::mc_pll_bndy_bucket_3 , "mc_pll_bndy_bucket_3" , MC_TYPE }, // 109 + { MC::mc_pll_bndy_bucket_4 , "mc_pll_bndy_bucket_4" , MC_TYPE }, // 110 + { MC::mc_pll_bndy_bucket_5 , "mc_pll_bndy_bucket_5" , MC_TYPE }, // 111 + { MC::mc_pll_func , "mc_pll_func" , MC_TYPE }, // 112 + { MC::mc_repr , "mc_repr" , MC_TYPE }, // 113 + { MC::mc_iom01_repr , "mc_iom01_repr" , MC_TYPE }, // 114 + { MC::mc_iom23_repr , "mc_iom23_repr" , MC_TYPE }, // 115 + { INVALID_RING , "invalid" , MC_TYPE }, // 116 + { INVALID_RING , "invalid" , MC_TYPE }, // 117 + { OB0::ob0_fure , "ob0_fure" , OB0_TYPE }, // 118 + { OB0::ob0_gptr , "ob0_gptr" , OB0_TYPE }, // 119 + { OB0::ob0_time , "ob0_time" , OB0_TYPE }, // 120 + { OB0::ob0_pll_gptr , "ob0_pll_gptr" , OB0_TYPE }, // 121 + { OB0::ob0_pll_bndy , "ob0_pll_bndy" , OB0_TYPE }, // 122 + { OB0::ob0_pll_func , "ob0_pll_func" , OB0_TYPE }, // 123 + { OB0::ob0_repr , "ob0_repr" , OB0_TYPE }, // 124 + { INVALID_RING , "invalid" , OB0_TYPE }, // 125 + { INVALID_RING , "invalid" , OB0_TYPE }, // 126 + { OB1::ob1_fure , "ob1_fure" , OB1_TYPE }, // 127 + { OB1::ob1_gptr , "ob1_gptr" , OB1_TYPE }, // 128 + { OB1::ob1_time , "ob1_time" , OB1_TYPE }, // 129 + { OB1::ob1_pll_gptr , "ob1_pll_gptr" , OB1_TYPE }, // 130 + { OB1::ob1_pll_bndy , "ob1_pll_bndy" , OB1_TYPE }, // 131 + { OB1::ob1_pll_func , "ob1_pll_func" , OB1_TYPE }, // 132 + { OB1::ob1_repr , "ob1_repr" , OB1_TYPE }, // 133 + { INVALID_RING , "invalid" , OB1_TYPE }, // 134 + { INVALID_RING , "invalid" , OB1_TYPE }, // 135 + { OB2::ob2_fure , "ob2_fure" , OB2_TYPE }, // 136 + { OB2::ob2_gptr , "ob2_gptr" , OB2_TYPE }, // 137 + { OB2::ob2_time , "ob2_time" , OB2_TYPE }, // 138 + { OB2::ob2_pll_gptr , "ob2_pll_gptr" , OB2_TYPE }, // 139 + { OB2::ob2_pll_bndy , "ob2_pll_bndy" , OB2_TYPE }, // 140 + { OB2::ob2_pll_func , "ob2_pll_func" , OB2_TYPE }, // 141 + { OB2::ob2_repr , "ob2_repr" , OB2_TYPE }, // 142 + { INVALID_RING , "invalid" , OB2_TYPE }, // 143 + { INVALID_RING , "invalid" , OB2_TYPE }, // 144 + { OB3::ob3_fure , "ob3_fure" , OB3_TYPE }, // 145 + { OB3::ob3_gptr , "ob3_gptr" , OB3_TYPE }, // 146 + { OB3::ob3_time , "ob3_time" , OB3_TYPE }, // 147 + { OB3::ob3_pll_gptr , "ob3_pll_gptr" , OB3_TYPE }, // 148 + { OB3::ob3_pll_bndy , "ob3_pll_bndy" , OB3_TYPE }, // 149 + { OB3::ob3_pll_func , "ob3_pll_func" , OB3_TYPE }, // 150 + { OB3::ob3_repr , "ob3_repr" , OB3_TYPE }, // 151 + { INVALID_RING , "invalid" , OB3_TYPE }, // 152 + { INVALID_RING , "invalid" , OB3_TYPE }, // 153 + { PCI0::pci0_fure , "pci0_fure" , PCI0_TYPE }, // 154 + { PCI0::pci0_gptr , "pci0_gptr" , PCI0_TYPE }, // 155 + { PCI0::pci0_time , "pci0_time" , PCI0_TYPE }, // 156 + { PCI0::pci0_pll_bndy , "pci0_pll_bndy" , PCI0_TYPE }, // 157 + { PCI0::pci0_pll_gptr , "pci0_pll_gptr" , PCI0_TYPE }, // 158 + { PCI0::pci0_repr , "pci0_repr" , PCI0_TYPE }, // 159 + { PCI1::pci1_fure , "pci1_fure" , PCI1_TYPE }, // 160 + { PCI1::pci1_gptr , "pci1_gptr" , PCI1_TYPE }, // 161 + { PCI1::pci1_time , "pci1_time" , PCI1_TYPE }, // 162 + { PCI1::pci1_pll_bndy , "pci1_pll_bndy" , PCI1_TYPE }, // 163 + { PCI1::pci1_pll_gptr , "pci1_pll_gptr" , PCI1_TYPE }, // 164 + { PCI1::pci1_repr , "pci1_repr" , PCI1_TYPE }, // 165 + { PCI2::pci2_fure , "pci2_fure" , PCI2_TYPE }, // 166 + { PCI2::pci2_gptr , "pci2_gptr" , PCI2_TYPE }, // 167 + { PCI2::pci2_time , "pci2_time" , PCI2_TYPE }, // 168 + { PCI2::pci2_pll_bndy , "pci2_pll_bndy" , PCI2_TYPE }, // 169 + { PCI2::pci2_pll_gptr , "pci2_pll_gptr" , PCI2_TYPE }, // 170 + { PCI2::pci2_repr , "pci2_repr" , PCI2_TYPE }, // 171 + { EQ::eq_fure , "eq_fure" , EQ_TYPE }, // 172 + { EQ::eq_gptr , "eq_gptr" , EQ_TYPE }, // 173 + { EQ::eq_time , "eq_time" , EQ_TYPE }, // 174 + { EQ::eq_mode , "eq_mode" , EQ_TYPE }, // 175 + { EQ::ex_l3_fure , "ex_l3_fure" , EQ_TYPE }, // 176 + { EQ::ex_l3_gptr , "ex_l3_gptr" , EQ_TYPE }, // 177 + { EQ::ex_l3_time , "ex_l3_time" , EQ_TYPE }, // 178 + { EQ::ex_l2_mode , "ex_l2_mode" , EQ_TYPE }, // 179 + { EQ::ex_l2_fure , "ex_l2_fure" , EQ_TYPE }, // 180 + { EQ::ex_l2_gptr , "ex_l2_gptr" , EQ_TYPE }, // 181 + { EQ::ex_l2_time , "ex_l2_time" , EQ_TYPE }, // 182 + { EQ::ex_l3_refr_fure , "ex_l3_refr_fure" , EQ_TYPE }, // 183 + { EQ::ex_l3_refr_gptr , "ex_l3_refr_gptr" , EQ_TYPE }, // 184 + { EQ::ex_l3_refr_time , "ex_l3_refr_time" , EQ_TYPE }, // 185 + { EQ::eq_ana_func , "eq_ana_func" , EQ_TYPE }, // 186 + { EQ::eq_ana_gptr , "eq_ana_gptr" , EQ_TYPE }, // 187 + { EQ::eq_dpll_func , "eq_dpll_func" , EQ_TYPE }, // 188 + { EQ::eq_dpll_gptr , "eq_dpll_gptr" , EQ_TYPE }, // 189 + { EQ::eq_dpll_mode , "eq_dpll_mode" , EQ_TYPE }, // 190 + { EQ::eq_ana_bndy , "eq_ana_bndy" , EQ_TYPE }, // 191 + { EQ::eq_ana_bndy_bucket_0 , "eq_ana_bndy_bucket_0" , EQ_TYPE }, // 192 + { EQ::eq_ana_bndy_bucket_1 , "eq_ana_bndy_bucket_1" , EQ_TYPE }, // 193 + { EQ::eq_ana_bndy_bucket_2 , "eq_ana_bndy_bucket_2" , EQ_TYPE }, // 194 + { EQ::eq_ana_bndy_bucket_3 , "eq_ana_bndy_bucket_3" , EQ_TYPE }, // 195 + { EQ::eq_ana_bndy_bucket_4 , "eq_ana_bndy_bucket_4" , EQ_TYPE }, // 196 + { EQ::eq_ana_bndy_bucket_5 , "eq_ana_bndy_bucket_5" , EQ_TYPE }, // 197 + { EQ::eq_ana_bndy_bucket_6 , "eq_ana_bndy_bucket_6" , EQ_TYPE }, // 198 + { EQ::eq_ana_bndy_bucket_7 , "eq_ana_bndy_bucket_7" , EQ_TYPE }, // 199 + { EQ::eq_ana_bndy_bucket_8 , "eq_ana_bndy_bucket_8" , EQ_TYPE }, // 200 + { EQ::eq_ana_bndy_bucket_9 , "eq_ana_bndy_bucket_9" , EQ_TYPE }, // 201 + { EQ::eq_ana_bndy_bucket_10 , "eq_ana_bndy_bucket_10" , EQ_TYPE }, // 202 + { EQ::eq_ana_bndy_bucket_11 , "eq_ana_bndy_bucket_11" , EQ_TYPE }, // 203 + { EQ::eq_ana_bndy_bucket_12 , "eq_ana_bndy_bucket_12" , EQ_TYPE }, // 204 + { EQ::eq_ana_bndy_bucket_13 , "eq_ana_bndy_bucket_13" , EQ_TYPE }, // 205 + { EQ::eq_ana_bndy_bucket_14 , "eq_ana_bndy_bucket_14" , EQ_TYPE }, // 206 + { EQ::eq_ana_bndy_bucket_15 , "eq_ana_bndy_bucket_15" , EQ_TYPE }, // 207 + { EQ::eq_ana_bndy_bucket_16 , "eq_ana_bndy_bucket_16" , EQ_TYPE }, // 208 + { EQ::eq_ana_bndy_bucket_17 , "eq_ana_bndy_bucket_17" , EQ_TYPE }, // 209 + { EQ::eq_ana_bndy_bucket_18 , "eq_ana_bndy_bucket_18" , EQ_TYPE }, // 210 + { EQ::eq_ana_bndy_bucket_19 , "eq_ana_bndy_bucket_19" , EQ_TYPE }, // 211 + { EQ::eq_ana_bndy_bucket_20 , "eq_ana_bndy_bucket_20" , EQ_TYPE }, // 212 + { EQ::eq_ana_bndy_bucket_21 , "eq_ana_bndy_bucket_21" , EQ_TYPE }, // 213 + { EQ::eq_ana_bndy_bucket_22 , "eq_ana_bndy_bucket_22" , EQ_TYPE }, // 214 + { EQ::eq_ana_bndy_bucket_23 , "eq_ana_bndy_bucket_23" , EQ_TYPE }, // 215 + { EQ::eq_ana_bndy_bucket_24 , "eq_ana_bndy_bucket_24" , EQ_TYPE }, // 216 + { EQ::eq_ana_bndy_bucket_25 , "eq_ana_bndy_bucket_25" , EQ_TYPE }, // 217 + { EQ::eq_ana_bndy_l3dcc_bucket_26 , "eq_ana_bndy_l3dcc_bucket_26" , EQ_TYPE }, // 218 + { EQ::eq_ana_mode , "eq_ana_mode" , EQ_TYPE }, // 219 + { EQ::eq_repr , "eq_repr" , EQ_TYPE }, // 220 + { EQ::ex_l3_repr , "ex_l3_repr" , EQ_TYPE }, // 221 + { EQ::ex_l2_repr , "ex_l2_repr" , EQ_TYPE }, // 222 + { EQ::ex_l3_refr_repr , "ex_l3_refr_repr" , EQ_TYPE }, // 223 + { EC::ec_func , "ec_func" , EC_TYPE }, // 224 + { EC::ec_gptr , "ec_gptr" , EC_TYPE }, // 225 + { EC::ec_time , "ec_time" , EC_TYPE }, // 226 + { EC::ec_mode , "ec_mode" , EC_TYPE }, // 227 + { EC::ec_repr , "ec_repr" , EC_TYPE }, // 228 }; #endif - - #ifdef __PPE__ static const ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] = { - // Pervasive Ring - {PERV::perv_fure, PERV_TYPE}, // 0 - {PERV::perv_gptr, PERV_TYPE}, // 1 - {PERV::perv_time, PERV_TYPE}, // 2 - {PERV::occ_fure, PERV_TYPE}, // 3 - {PERV::occ_gptr, PERV_TYPE}, // 4 - {PERV::occ_time, PERV_TYPE}, // 5 - {PERV::perv_ana_func, PERV_TYPE}, // 6 - {PERV::perv_ana_gptr, PERV_TYPE}, // 7 - {PERV::perv_pll_gptr, PERV_TYPE}, // 8 - {PERV::perv_pll_bndy, PERV_TYPE}, // 9 - {PERV::perv_pll_bndy_bucket_1, PERV_TYPE}, // 10 - {PERV::perv_pll_bndy_bucket_2, PERV_TYPE}, // 11 - {PERV::perv_pll_bndy_bucket_3, PERV_TYPE}, // 12 - {PERV::perv_pll_bndy_bucket_4, PERV_TYPE}, // 13 - {PERV::perv_pll_bndy_bucket_5, PERV_TYPE}, // 14 - {PERV::perv_pll_func, PERV_TYPE}, // 15 - {PERV::perv_pibnet_gptr, PERV_TYPE}, // 16 - {PERV::perv_pibnet_time, PERV_TYPE}, // 17 - {PERV::perv_repr, PERV_TYPE}, // 18 - {PERV::occ_repr, PERV_TYPE}, // 19 - {PERV::perv_pibnet_repr, PERV_TYPE}, // 20 - - // Nest N0 Ring - {N0::n0_fure, N0_TYPE}, // 21 - {N0::n0_gptr, N0_TYPE}, // 22 - {N0::n0_time, N0_TYPE}, // 23 - {N0::n0_nx_fure, N0_TYPE}, // 24 - {N0::n0_nx_gptr, N0_TYPE}, // 25 - {N0::n0_nx_time, N0_TYPE}, // 26 - {N0::n0_cxa0_fure, N0_TYPE}, // 27 - {N0::n0_cxa0_gptr, N0_TYPE}, // 28 - {N0::n0_cxa0_time, N0_TYPE}, // 29 - {N0::n0_repr, N0_TYPE}, // 30 - {N0::n0_nx_repr, N0_TYPE}, // 31 - {N0::n0_cxa0_repr, N0_TYPE}, // 32 - - // Nest N1 Ring - {N1::n1_fure, N1_TYPE}, // 33 - {N1::n1_gptr, N1_TYPE}, // 34 - {N1::n1_time, N1_TYPE}, // 35 - {N1::n1_ioo0_fure, N1_TYPE}, // 36 - {N1::n1_ioo0_gptr, N1_TYPE}, // 37 - {N1::n1_ioo0_time, N1_TYPE}, // 38 - {N1::n1_ioo1_fure, N1_TYPE}, // 39 - {N1::n1_ioo1_gptr, N1_TYPE}, // 40 - {N1::n1_ioo1_time, N1_TYPE}, // 41 - {N1::n1_mcs23_fure, N1_TYPE}, // 42 - {N1::n1_mcs23_gptr, N1_TYPE}, // 43 - {N1::n1_mcs23_time, N1_TYPE}, // 44 - {N1::n1_repr, N1_TYPE}, // 45 - {N1::n1_ioo0_repr, N1_TYPE}, // 46 - {N1::n1_ioo1_repr, N1_TYPE}, // 47 - {N1::n1_mcs23_repr, N1_TYPE}, // 48 - - // Nest N2 Ring - {N2::n2_fure, N2_TYPE}, // 49 - {N2::n2_gptr, N2_TYPE}, // 50 - {N2::n2_time, N2_TYPE}, // 51 - {N2::n2_cxa1_fure, N2_TYPE}, // 52 - {N2::n2_cxa1_gptr, N2_TYPE}, // 53 - {N2::n2_cxa1_time, N2_TYPE}, // 54 - {N2::n2_psi_fure, N2_TYPE}, // 55 - {N2::n2_psi_gptr, N2_TYPE}, // 56 - {N2::n2_psi_time, N2_TYPE}, // 57 - {N2::n2_repr, N2_TYPE}, // 58 - {N2::n2_cxa1_repr, N2_TYPE}, // 59 - {N2::n2_psi_repr, N2_TYPE}, // 60 - {INVALID_RING, N1_TYPE},// 61 // for future - - // Nest N3 Ring - {N3::n3_fure, N3_TYPE}, // 62 - {N3::n3_gptr, N3_TYPE}, // 63 - {N3::n3_time, N3_TYPE}, // 64 - {N3::n3_mcs01_fure, N3_TYPE}, // 65 - {N3::n3_mcs01_gptr, N3_TYPE}, // 66 - {N3::n3_mcs01_time, N3_TYPE}, // 67 - {N3::n3_np_fure, N3_TYPE}, // 68 - {N3::n3_np_gptr, N3_TYPE}, // 69 - {N3::n3_np_time, N3_TYPE}, // 70 - {N3::n3_repr, N3_TYPE}, // 71 - {N3::n3_mcs01_repr, N3_TYPE}, // 72 - {N3::n3_np_repr, N3_TYPE}, // 73 - {INVALID_RING, N3_TYPE}, // 74 // for future. - - // XB Ring - {XB::xb_fure, XB_TYPE}, // 75 - {XB::xb_gptr, XB_TYPE}, // 76 - {XB::xb_time, XB_TYPE}, // 77 - {XB::xb_io0_fure, XB_TYPE}, // 78 - {XB::xb_io0_gptr, XB_TYPE}, // 79 - {XB::xb_io0_time, XB_TYPE}, // 80 - {XB::xb_io1_fure, XB_TYPE}, // 81 - {XB::xb_io1_gptr, XB_TYPE}, // 82 - {XB::xb_io1_time, XB_TYPE}, // 83 - {XB::xb_io2_fure, XB_TYPE}, // 84 - {XB::xb_io2_gptr, XB_TYPE}, // 85 - {XB::xb_io2_time, XB_TYPE}, // 86 - {XB::xb_pll_gptr, XB_TYPE}, // 87 - {XB::xb_pll_bndy, XB_TYPE}, // 88 - {XB::xb_pll_bndy_bucket_1, XB_TYPE}, // 89 - {XB::xb_pll_bndy_bucket_2, XB_TYPE}, // 90 - {XB::xb_pll_bndy_bucket_3, XB_TYPE}, // 91 - {XB::xb_pll_bndy_bucket_4, XB_TYPE}, // 92 - {XB::xb_pll_bndy_bucket_5, XB_TYPE}, // 93 - {XB::xb_pll_func, XB_TYPE}, // 94 - {XB::xb_repr, XB_TYPE}, // 95 - {XB::xb_io0_repr, XB_TYPE}, // 96 - {XB::xb_io1_repr, XB_TYPE}, // 97 - {XB::xb_io2_repr, XB_TYPE}, // 98 - {INVALID_RING, XB_TYPE}, // 99 // for future. - {INVALID_RING, XB_TYPE}, // 100 // for future. - - // MC Ring - {MC::mc_fure, MC_TYPE}, // 101 - {MC::mc_gptr, MC_TYPE}, // 102 - {MC::mc_time, MC_TYPE}, // 103 - {MC::mc_iom01_fure, MC_TYPE}, // 104 - {MC::mc_iom01_gptr, MC_TYPE}, // 105 - {MC::mc_iom01_time, MC_TYPE}, // 106 - {MC::mc_iom23_fure, MC_TYPE}, // 107 - {MC::mc_iom23_gptr, MC_TYPE}, // 108 - {MC::mc_iom23_time, MC_TYPE}, // 109 - {MC::mc_pll_gptr, MC_TYPE}, // 110 - {MC::mc_pll_bndy, MC_TYPE}, // 111 - {MC::mc_pll_bndy_bucket_1, MC_TYPE}, // 112 - {MC::mc_pll_bndy_bucket_2, MC_TYPE}, // 113 - {MC::mc_pll_bndy_bucket_3, MC_TYPE}, // 114 - {MC::mc_pll_bndy_bucket_4, MC_TYPE}, // 115 - {MC::mc_pll_bndy_bucket_5, MC_TYPE}, // 116 - {MC::mc_pll_func, MC_TYPE}, // 117 - {MC::mc_repr, MC_TYPE}, // 118 - {MC::mc_iom01_repr, MC_TYPE}, // 119 - {MC::mc_iom23_repr, MC_TYPE}, // 120 - {INVALID_RING, MC_TYPE}, // 121 // for future. - {INVALID_RING, MC_TYPE}, // 122 // for future. - - // OB Ring - {OB0::ob0_fure, OB0_TYPE}, // 123 - {OB0::ob0_gptr, OB0_TYPE}, // 124 - {OB0::ob0_time, OB0_TYPE}, // 125 - {OB0::ob0_pll_gptr, OB0_TYPE}, // 126 - {OB0::ob0_pll_bndy, OB0_TYPE}, // 127 - {OB0::ob0_pll_bndy_bucket_1, OB0_TYPE}, // 128 - {OB0::ob0_pll_bndy_bucket_2, OB0_TYPE}, // 129 - {OB0::ob0_pll_bndy_bucket_3, OB0_TYPE}, // 130 - {OB0::ob0_pll_bndy_bucket_4, OB0_TYPE}, // 131 - {OB0::ob0_pll_bndy_bucket_5, OB0_TYPE}, // 132 - {OB0::ob0_pll_func, OB0_TYPE}, // 133 - {OB0::ob0_repr, OB0_TYPE}, // 134 - {INVALID_RING, OB0_TYPE}, // 135 // for future. - {INVALID_RING, OB0_TYPE}, // 136 // for future. - - {OB1::ob1_fure, OB1_TYPE}, // 137 - {OB1::ob1_gptr, OB1_TYPE}, // 138 - {OB1::ob1_time, OB1_TYPE}, // 139 - {OB1::ob1_pll_gptr, OB1_TYPE}, // 140 - {OB1::ob1_pll_bndy, OB1_TYPE}, // 141 - {OB1::ob1_pll_bndy_bucket_1, OB1_TYPE}, // 142 - {OB1::ob1_pll_bndy_bucket_2, OB1_TYPE}, // 143 - {OB1::ob1_pll_bndy_bucket_3, OB1_TYPE}, // 144 - {OB1::ob1_pll_bndy_bucket_4, OB1_TYPE}, // 145 - {OB1::ob1_pll_bndy_bucket_5, OB1_TYPE}, // 146 - {OB1::ob1_pll_func, OB1_TYPE}, // 147 - {OB1::ob1_repr, OB1_TYPE}, // 148 - {INVALID_RING, OB1_TYPE}, // 149 // for future. - {INVALID_RING, OB1_TYPE}, // 150 // for future. - - {OB2::ob2_fure, OB2_TYPE}, // 151 - {OB2::ob2_gptr, OB2_TYPE}, // 152 - {OB2::ob2_time, OB2_TYPE}, // 153 - {OB2::ob2_pll_gptr, OB2_TYPE}, // 154 - {OB2::ob2_pll_bndy, OB2_TYPE}, // 155 - {OB2::ob2_pll_bndy_bucket_1, OB2_TYPE}, // 156 - {OB2::ob2_pll_bndy_bucket_2, OB2_TYPE}, // 157 - {OB2::ob2_pll_bndy_bucket_3, OB2_TYPE}, // 158 - {OB2::ob2_pll_bndy_bucket_4, OB2_TYPE}, // 159 - {OB2::ob2_pll_bndy_bucket_5, OB2_TYPE}, // 160 - {OB2::ob2_pll_func, OB2_TYPE}, // 161 - {OB2::ob2_repr, OB2_TYPE}, // 162 - {INVALID_RING, OB2_TYPE}, // 163 // for future. - {INVALID_RING, OB2_TYPE}, // 164 // for future. - - {OB3::ob3_fure, OB3_TYPE}, // 165 - {OB3::ob3_gptr, OB3_TYPE}, // 166 - {OB3::ob3_time, OB3_TYPE}, // 167 - {OB3::ob3_pll_gptr, OB3_TYPE}, // 168 - {OB3::ob3_pll_bndy, OB3_TYPE}, // 169 - {OB3::ob3_pll_bndy_bucket_1, OB3_TYPE}, // 170 - {OB3::ob3_pll_bndy_bucket_2, OB3_TYPE}, // 171 - {OB3::ob3_pll_bndy_bucket_3, OB3_TYPE}, // 172 - {OB3::ob3_pll_bndy_bucket_4, OB3_TYPE}, // 173 - {OB3::ob3_pll_bndy_bucket_5, OB3_TYPE}, // 174 - {OB3::ob3_pll_func, OB3_TYPE}, // 175 - {OB3::ob3_repr, OB3_TYPE}, // 176 - {INVALID_RING, OB3_TYPE}, // 177 // for future. - {INVALID_RING, OB3_TYPE}, // 178 // for future. - - // PCI0 Ring - {PCI0::pci0_fure, PCI0_TYPE}, // 179 - {PCI0::pci0_gptr, PCI0_TYPE}, // 180 - {PCI0::pci0_time, PCI0_TYPE}, // 181 - {PCI0::pci0_pll_func, PCI0_TYPE}, // 182 - {PCI0::pci0_pll_gptr, PCI0_TYPE}, // 183 - {PCI0::pci0_repr, PCI0_TYPE}, // 184 - // PCI1 Ring - {PCI1::pci1_fure, PCI1_TYPE}, // 185 - {PCI1::pci1_gptr, PCI1_TYPE}, // 186 - {PCI1::pci1_time, PCI1_TYPE}, // 187 - {PCI1::pci1_pll_func, PCI1_TYPE}, // 188 - {PCI1::pci1_pll_gptr, PCI1_TYPE}, // 189 - {PCI1::pci1_repr, PCI1_TYPE}, // 190 - // PCI2 Ring - {PCI2::pci2_fure, PCI2_TYPE}, // 191 - {PCI2::pci2_gptr, PCI2_TYPE}, // 192 - {PCI2::pci2_time, PCI2_TYPE}, // 193 - {PCI2::pci2_pll_func, PCI2_TYPE}, // 194 - {PCI2::pci2_pll_gptr, PCI2_TYPE}, // 195 - {PCI2::pci2_repr, PCI2_TYPE}, // 196 - - // EQ Ring - {EQ::eq_fure, EQ_TYPE}, // 197 - {EQ::eq_gptr, EQ_TYPE}, // 198 - {EQ::eq_time, EQ_TYPE}, // 199 - {EQ::eq_mode, EQ_TYPE}, // 200 - {EQ::ex_l3_fure, EQ_TYPE}, // 201 - {EQ::ex_l3_gptr, EQ_TYPE}, // 202 - {EQ::ex_l3_time, EQ_TYPE}, // 203 - {EQ::ex_l2_mode, EQ_TYPE}, // 204 - {EQ::ex_l2_fure, EQ_TYPE}, // 205 - {EQ::ex_l2_gptr, EQ_TYPE}, // 206 - {EQ::ex_l2_time, EQ_TYPE}, // 207 - {EQ::ex_l3_refr_fure, EQ_TYPE}, // 208 - {EQ::ex_l3_refr_gptr, EQ_TYPE}, // 209 - {EQ::ex_l3_refr_time, EQ_TYPE}, // 210 - {EQ::eq_ana_func, EQ_TYPE}, // 211 - {EQ::eq_ana_gptr, EQ_TYPE}, // 212 - {EQ::eq_dpll_func, EQ_TYPE}, // 213 - {EQ::eq_dpll_gptr, EQ_TYPE}, // 214 - {EQ::eq_dpll_mode, EQ_TYPE}, // 215 - {EQ::eq_ana_bndy, EQ_TYPE}, // 216 - {EQ::eq_ana_bndy_bucket_0, EQ_TYPE}, // 217 - {EQ::eq_ana_bndy_bucket_1, EQ_TYPE}, // 218 - {EQ::eq_ana_bndy_bucket_2, EQ_TYPE}, // 219 - {EQ::eq_ana_bndy_bucket_3, EQ_TYPE}, // 220 - {EQ::eq_ana_bndy_bucket_4, EQ_TYPE}, // 221 - {EQ::eq_ana_bndy_bucket_5, EQ_TYPE}, // 222 - {EQ::eq_ana_bndy_bucket_6, EQ_TYPE}, // 223 - {EQ::eq_ana_bndy_bucket_7, EQ_TYPE}, // 224 - {EQ::eq_ana_bndy_bucket_8, EQ_TYPE}, // 225 - {EQ::eq_ana_bndy_bucket_9, EQ_TYPE}, // 226 - {EQ::eq_ana_bndy_bucket_10, EQ_TYPE}, // 227 - {EQ::eq_ana_bndy_bucket_11, EQ_TYPE}, // 228 - {EQ::eq_ana_bndy_bucket_12, EQ_TYPE}, // 229 - {EQ::eq_ana_bndy_bucket_13, EQ_TYPE}, // 230 - {EQ::eq_ana_bndy_bucket_14, EQ_TYPE}, // 231 - {EQ::eq_ana_bndy_bucket_15, EQ_TYPE}, // 232 - {EQ::eq_ana_bndy_bucket_16, EQ_TYPE}, // 233 - {EQ::eq_ana_bndy_bucket_17, EQ_TYPE}, // 234 - {EQ::eq_ana_bndy_bucket_18, EQ_TYPE}, // 235 - {EQ::eq_ana_bndy_bucket_19, EQ_TYPE}, // 236 - {EQ::eq_ana_bndy_bucket_20, EQ_TYPE}, // 237 - {EQ::eq_ana_bndy_bucket_21, EQ_TYPE}, // 238 - {EQ::eq_ana_bndy_bucket_22, EQ_TYPE}, // 239 - {EQ::eq_ana_bndy_bucket_23, EQ_TYPE}, // 240 - {EQ::eq_ana_bndy_bucket_24, EQ_TYPE}, // 241 - {EQ::eq_ana_bndy_bucket_25, EQ_TYPE}, // 242 - {EQ::eq_ana_bndy_l3dcc_bucket_26, EQ_TYPE}, // 243 - - {EQ::eq_ana_mode, EQ_TYPE}, // 244 - {EQ::eq_repr, EQ_TYPE}, // 245 - {EQ::ex_l3_repr, EQ_TYPE}, // 246 - {EQ::ex_l2_repr, EQ_TYPE}, // 247 - {EQ::ex_l3_refr_repr, EQ_TYPE}, // 248 - - // Core Ring - {EC::ec_func, EC_TYPE}, // 249 - {EC::ec_gptr, EC_TYPE}, // 250 - {EC::ec_time, EC_TYPE}, // 251 - {EC::ec_mode, EC_TYPE}, // 252 - {EC::ec_repr, EC_TYPE} // 253 + { PERV::perv_fure , PERV_TYPE }, // 0 + { PERV::perv_gptr , PERV_TYPE }, // 1 + { PERV::perv_time , PERV_TYPE }, // 2 + { PERV::occ_fure , PERV_TYPE }, // 3 + { PERV::occ_gptr , PERV_TYPE }, // 4 + { PERV::occ_time , PERV_TYPE }, // 5 + { PERV::perv_ana_func , PERV_TYPE }, // 6 + { PERV::perv_ana_gptr , PERV_TYPE }, // 7 + { PERV::perv_pll_gptr , PERV_TYPE }, // 8 + { PERV::perv_pll_bndy , PERV_TYPE }, // 9 + { PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 10 + { PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 11 + { PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 12 + { PERV::perv_pll_bndy_bucket_4 , PERV_TYPE }, // 13 + { PERV::perv_pll_bndy_bucket_5 , PERV_TYPE }, // 14 + { PERV::perv_pll_func , PERV_TYPE }, // 15 + { PERV::perv_pibnet_gptr , PERV_TYPE }, // 16 + { PERV::perv_pibnet_time , PERV_TYPE }, // 17 + { PERV::perv_repr , PERV_TYPE }, // 18 + { PERV::occ_repr , PERV_TYPE }, // 19 + { PERV::perv_pibnet_repr , PERV_TYPE }, // 20 + { N0::n0_fure , N0_TYPE }, // 21 + { N0::n0_gptr , N0_TYPE }, // 22 + { N0::n0_time , N0_TYPE }, // 23 + { N0::n0_nx_fure , N0_TYPE }, // 24 + { N0::n0_nx_gptr , N0_TYPE }, // 25 + { N0::n0_nx_time , N0_TYPE }, // 26 + { N0::n0_cxa0_fure , N0_TYPE }, // 27 + { N0::n0_cxa0_gptr , N0_TYPE }, // 28 + { N0::n0_cxa0_time , N0_TYPE }, // 29 + { N0::n0_repr , N0_TYPE }, // 30 + { N0::n0_nx_repr , N0_TYPE }, // 31 + { N0::n0_cxa0_repr , N0_TYPE }, // 32 + { N1::n1_fure , N1_TYPE }, // 33 + { N1::n1_gptr , N1_TYPE }, // 34 + { N1::n1_time , N1_TYPE }, // 35 + { N1::n1_ioo0_fure , N1_TYPE }, // 36 + { N1::n1_ioo0_gptr , N1_TYPE }, // 37 + { N1::n1_ioo0_time , N1_TYPE }, // 38 + { N1::n1_ioo1_fure , N1_TYPE }, // 39 + { N1::n1_ioo1_gptr , N1_TYPE }, // 40 + { N1::n1_ioo1_time , N1_TYPE }, // 41 + { N1::n1_mcs23_fure , N1_TYPE }, // 42 + { N1::n1_mcs23_gptr , N1_TYPE }, // 43 + { N1::n1_mcs23_time , N1_TYPE }, // 44 + { N1::n1_repr , N1_TYPE }, // 45 + { N1::n1_ioo0_repr , N1_TYPE }, // 46 + { N1::n1_ioo1_repr , N1_TYPE }, // 47 + { N1::n1_mcs23_repr , N1_TYPE }, // 48 + { N2::n2_fure , N2_TYPE }, // 49 + { N2::n2_gptr , N2_TYPE }, // 50 + { N2::n2_time , N2_TYPE }, // 51 + { N2::n2_cxa1_fure , N2_TYPE }, // 52 + { N2::n2_cxa1_gptr , N2_TYPE }, // 53 + { N2::n2_cxa1_time , N2_TYPE }, // 54 + { N2::n2_psi_fure , N2_TYPE }, // 55 + { N2::n2_psi_gptr , N2_TYPE }, // 56 + { N2::n2_psi_time , N2_TYPE }, // 57 + { N2::n2_repr , N2_TYPE }, // 58 + { N2::n2_cxa1_repr , N2_TYPE }, // 59 + { N2::n2_psi_repr , N2_TYPE }, // 60 + { INVALID_RING , N2_TYPE }, // 61 + { N3::n3_fure , N3_TYPE }, // 62 + { N3::n3_gptr , N3_TYPE }, // 63 + { N3::n3_time , N3_TYPE }, // 64 + { N3::n3_mcs01_fure , N3_TYPE }, // 65 + { N3::n3_mcs01_gptr , N3_TYPE }, // 66 + { N3::n3_mcs01_time , N3_TYPE }, // 67 + { N3::n3_np_fure , N3_TYPE }, // 68 + { N3::n3_np_gptr , N3_TYPE }, // 69 + { N3::n3_np_time , N3_TYPE }, // 70 + { N3::n3_repr , N3_TYPE }, // 71 + { N3::n3_mcs01_repr , N3_TYPE }, // 72 + { N3::n3_np_repr , N3_TYPE }, // 73 + { INVALID_RING , N3_TYPE }, // 74 + { XB::xb_fure , XB_TYPE }, // 75 + { XB::xb_gptr , XB_TYPE }, // 76 + { XB::xb_time , XB_TYPE }, // 77 + { XB::xb_io0_fure , XB_TYPE }, // 78 + { XB::xb_io0_gptr , XB_TYPE }, // 79 + { XB::xb_io0_time , XB_TYPE }, // 80 + { XB::xb_io1_fure , XB_TYPE }, // 81 + { XB::xb_io1_gptr , XB_TYPE }, // 82 + { XB::xb_io1_time , XB_TYPE }, // 83 + { XB::xb_io2_fure , XB_TYPE }, // 84 + { XB::xb_io2_gptr , XB_TYPE }, // 85 + { XB::xb_io2_time , XB_TYPE }, // 86 + { XB::xb_pll_gptr , XB_TYPE }, // 87 + { XB::xb_pll_bndy , XB_TYPE }, // 88 + { XB::xb_pll_func , XB_TYPE }, // 89 + { XB::xb_repr , XB_TYPE }, // 90 + { XB::xb_io0_repr , XB_TYPE }, // 91 + { XB::xb_io1_repr , XB_TYPE }, // 92 + { XB::xb_io2_repr , XB_TYPE }, // 93 + { INVALID_RING , XB_TYPE }, // 94 + { INVALID_RING , XB_TYPE }, // 95 + { MC::mc_fure , MC_TYPE }, // 96 + { MC::mc_gptr , MC_TYPE }, // 97 + { MC::mc_time , MC_TYPE }, // 98 + { MC::mc_iom01_fure , MC_TYPE }, // 99 + { MC::mc_iom01_gptr , MC_TYPE }, // 100 + { MC::mc_iom01_time , MC_TYPE }, // 101 + { MC::mc_iom23_fure , MC_TYPE }, // 102 + { MC::mc_iom23_gptr , MC_TYPE }, // 103 + { MC::mc_iom23_time , MC_TYPE }, // 104 + { MC::mc_pll_gptr , MC_TYPE }, // 105 + { MC::mc_pll_bndy , MC_TYPE }, // 106 + { MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 107 + { MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 108 + { MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 109 + { MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 110 + { MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 111 + { MC::mc_pll_func , MC_TYPE }, // 112 + { MC::mc_repr , MC_TYPE }, // 113 + { MC::mc_iom01_repr , MC_TYPE }, // 114 + { MC::mc_iom23_repr , MC_TYPE }, // 115 + { INVALID_RING , MC_TYPE }, // 116 + { INVALID_RING , MC_TYPE }, // 117 + { OB0::ob0_fure , OB0_TYPE }, // 118 + { OB0::ob0_gptr , OB0_TYPE }, // 119 + { OB0::ob0_time , OB0_TYPE }, // 120 + { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 + { OB0::ob0_pll_bndy , OB0_TYPE }, // 122 + { OB0::ob0_pll_func , OB0_TYPE }, // 123 + { OB0::ob0_repr , OB0_TYPE }, // 124 + { INVALID_RING , OB0_TYPE }, // 125 + { INVALID_RING , OB0_TYPE }, // 126 + { OB1::ob1_fure , OB1_TYPE }, // 127 + { OB1::ob1_gptr , OB1_TYPE }, // 128 + { OB1::ob1_time , OB1_TYPE }, // 129 + { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 + { OB1::ob1_pll_bndy , OB1_TYPE }, // 131 + { OB1::ob1_pll_func , OB1_TYPE }, // 132 + { OB1::ob1_repr , OB1_TYPE }, // 133 + { INVALID_RING , OB1_TYPE }, // 134 + { INVALID_RING , OB1_TYPE }, // 135 + { OB2::ob2_fure , OB2_TYPE }, // 136 + { OB2::ob2_gptr , OB2_TYPE }, // 137 + { OB2::ob2_time , OB2_TYPE }, // 138 + { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 + { OB2::ob2_pll_bndy , OB2_TYPE }, // 140 + { OB2::ob2_pll_func , OB2_TYPE }, // 141 + { OB2::ob2_repr , OB2_TYPE }, // 142 + { INVALID_RING , OB2_TYPE }, // 143 + { INVALID_RING , OB2_TYPE }, // 144 + { OB3::ob3_fure , OB3_TYPE }, // 145 + { OB3::ob3_gptr , OB3_TYPE }, // 146 + { OB3::ob3_time , OB3_TYPE }, // 147 + { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 + { OB3::ob3_pll_bndy , OB3_TYPE }, // 149 + { OB3::ob3_pll_func , OB3_TYPE }, // 150 + { OB3::ob3_repr , OB3_TYPE }, // 151 + { INVALID_RING , OB3_TYPE }, // 152 + { INVALID_RING , OB3_TYPE }, // 153 + { PCI0::pci0_fure , PCI0_TYPE }, // 154 + { PCI0::pci0_gptr , PCI0_TYPE }, // 155 + { PCI0::pci0_time , PCI0_TYPE }, // 156 + { PCI0::pci0_pll_bndy , PCI0_TYPE }, // 157 + { PCI0::pci0_pll_gptr , PCI0_TYPE }, // 158 + { PCI0::pci0_repr , PCI0_TYPE }, // 159 + { PCI1::pci1_fure , PCI1_TYPE }, // 160 + { PCI1::pci1_gptr , PCI1_TYPE }, // 161 + { PCI1::pci1_time , PCI1_TYPE }, // 162 + { PCI1::pci1_pll_bndy , PCI1_TYPE }, // 163 + { PCI1::pci1_pll_gptr , PCI1_TYPE }, // 164 + { PCI1::pci1_repr , PCI1_TYPE }, // 165 + { PCI2::pci2_fure , PCI2_TYPE }, // 166 + { PCI2::pci2_gptr , PCI2_TYPE }, // 167 + { PCI2::pci2_time , PCI2_TYPE }, // 168 + { PCI2::pci2_pll_bndy , PCI2_TYPE }, // 169 + { PCI2::pci2_pll_gptr , PCI2_TYPE }, // 170 + { PCI2::pci2_repr , PCI2_TYPE }, // 171 + { EQ::eq_fure , EQ_TYPE }, // 172 + { EQ::eq_gptr , EQ_TYPE }, // 173 + { EQ::eq_time , EQ_TYPE }, // 174 + { EQ::eq_mode , EQ_TYPE }, // 175 + { EQ::ex_l3_fure , EQ_TYPE }, // 176 + { EQ::ex_l3_gptr , EQ_TYPE }, // 177 + { EQ::ex_l3_time , EQ_TYPE }, // 178 + { EQ::ex_l2_mode , EQ_TYPE }, // 179 + { EQ::ex_l2_fure , EQ_TYPE }, // 180 + { EQ::ex_l2_gptr , EQ_TYPE }, // 181 + { EQ::ex_l2_time , EQ_TYPE }, // 182 + { EQ::ex_l3_refr_fure , EQ_TYPE }, // 183 + { EQ::ex_l3_refr_gptr , EQ_TYPE }, // 184 + { EQ::ex_l3_refr_time , EQ_TYPE }, // 185 + { EQ::eq_ana_func , EQ_TYPE }, // 186 + { EQ::eq_ana_gptr , EQ_TYPE }, // 187 + { EQ::eq_dpll_func , EQ_TYPE }, // 188 + { EQ::eq_dpll_gptr , EQ_TYPE }, // 189 + { EQ::eq_dpll_mode , EQ_TYPE }, // 190 + { EQ::eq_ana_bndy , EQ_TYPE }, // 191 + { EQ::eq_ana_bndy_bucket_0 , EQ_TYPE }, // 192 + { EQ::eq_ana_bndy_bucket_1 , EQ_TYPE }, // 193 + { EQ::eq_ana_bndy_bucket_2 , EQ_TYPE }, // 194 + { EQ::eq_ana_bndy_bucket_3 , EQ_TYPE }, // 195 + { EQ::eq_ana_bndy_bucket_4 , EQ_TYPE }, // 196 + { EQ::eq_ana_bndy_bucket_5 , EQ_TYPE }, // 197 + { EQ::eq_ana_bndy_bucket_6 , EQ_TYPE }, // 198 + { EQ::eq_ana_bndy_bucket_7 , EQ_TYPE }, // 199 + { EQ::eq_ana_bndy_bucket_8 , EQ_TYPE }, // 200 + { EQ::eq_ana_bndy_bucket_9 , EQ_TYPE }, // 201 + { EQ::eq_ana_bndy_bucket_10 , EQ_TYPE }, // 202 + { EQ::eq_ana_bndy_bucket_11 , EQ_TYPE }, // 203 + { EQ::eq_ana_bndy_bucket_12 , EQ_TYPE }, // 204 + { EQ::eq_ana_bndy_bucket_13 , EQ_TYPE }, // 205 + { EQ::eq_ana_bndy_bucket_14 , EQ_TYPE }, // 206 + { EQ::eq_ana_bndy_bucket_15 , EQ_TYPE }, // 207 + { EQ::eq_ana_bndy_bucket_16 , EQ_TYPE }, // 208 + { EQ::eq_ana_bndy_bucket_17 , EQ_TYPE }, // 209 + { EQ::eq_ana_bndy_bucket_18 , EQ_TYPE }, // 210 + { EQ::eq_ana_bndy_bucket_19 , EQ_TYPE }, // 211 + { EQ::eq_ana_bndy_bucket_20 , EQ_TYPE }, // 212 + { EQ::eq_ana_bndy_bucket_21 , EQ_TYPE }, // 213 + { EQ::eq_ana_bndy_bucket_22 , EQ_TYPE }, // 214 + { EQ::eq_ana_bndy_bucket_23 , EQ_TYPE }, // 215 + { EQ::eq_ana_bndy_bucket_24 , EQ_TYPE }, // 216 + { EQ::eq_ana_bndy_bucket_25 , EQ_TYPE }, // 217 + { EQ::eq_ana_bndy_l3dcc_bucket_26 , EQ_TYPE }, // 218 + { EQ::eq_ana_mode , EQ_TYPE }, // 219 + { EQ::eq_repr , EQ_TYPE }, // 220 + { EQ::ex_l3_repr , EQ_TYPE }, // 221 + { EQ::ex_l2_repr , EQ_TYPE }, // 222 + { EQ::ex_l3_refr_repr , EQ_TYPE }, // 223 + { EC::ec_func , EC_TYPE }, // 224 + { EC::ec_gptr , EC_TYPE }, // 225 + { EC::ec_time , EC_TYPE }, // 226 + { EC::ec_mode , EC_TYPE }, // 227 + { EC::ec_repr , EC_TYPE }, // 228 }; #endif + #endif |
