summaryrefslogtreecommitdiffstats
path: root/arch/arm/cpu/armv7/omap5
Commit message (Collapse)AuthorAgeFilesLines
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-251-0/+3
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2Nishanth Menon2016-04-251-2/+0
| | | | | | | | | | | | | This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused. This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Expose do_set_iodelayNishanth Menon2016-03-271-2/+2
| | | | | | | | do_set_iodelay can now be used from board files based on needs of the platforms variation they have. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/DRA7: Split iodelay functionality into sub stepsNishanth Menon2016-03-271-14/+50
| | | | | | | | | | | | | | | | Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation. While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0Nishanth Menon2016-03-271-1/+43
| | | | | | | Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0Nishanth Menon2016-03-271-1/+15
| | | | | | | | | Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72x: Add support for detection of SR2.0Ravi Babu2016-03-273-0/+7
| | | | | | | | | Add support for detection of SR2.0 version of DRA72x family of processors. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Move emif settings to board specific filesLokesh Vutla2016-03-141-147/+2
| | | | | | | | | | The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Enable EEPROM supportLokesh Vutla2016-03-141-0/+1
| | | | | | | | Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: emif: Check for enable bits before updating leveling outputLokesh Vutla2016-03-141-8/+26
| | | | | | | | | Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: AM57xx: Add detection logic for AM57xx-evmKipisz, Steven2016-03-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current AM57xx evm supports both BeagleBoard-X15 (http://beagleboard.org/x15) and AM57xx EVM (http://www.ti.com/tool/tmdxevm5728). The AM572x EValuation Module(EVM) provides an affordable platform to quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. This EVM is based on the same BeagleBoard-X15 Chassis and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Since the EEPROM contents are compatible between the BeagleBoard-X15 and the AM57xx-evm, we add support for the detection logic to enable support for various user programmable scripting capability. NOTE: U-boot configuration is currently a superset of AM57xx evm and BeagleBoard-X15 and no additional configuration tweaking is needed. This change also sets up the stage for future support of TI AM57xx EVMs to the same base bootloader build. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: beagle_x15: Rename to indicate support for TI am57xx evmsKipisz, Steven2015-11-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does actually support two different platform configuration offered by TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728 (or more commonly known as AM5728-evm). Information about the TI AM57xx EVM can be found here http://www.ti.com/tool/tmdxevm5728 The EVM configuration is 1-1 compatible with BeagleBoard X15 with the additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Hence, we rename the beagle_x15 directory to am57xx to support TI EVMs that use the AM57xx processor. By doing this we have common code reuse. This sets the stage to have a common u-boot image solution for multiple TI EVMs such as that already done for am335x and am437x. This sets the stage for upcoming multiple TI EVMs that share the same code base. NOTE: Commit eae7ae185335 ("am437x: Add am57xx_evm_defconfig using CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm platform name. However, this ignored the potential confusion arising for users as a result. To prevent this, existing beagle_x15_defconfig is renamed as am57xx_evm_nodt_defconfig to denote that this is the "non device tree" configuration for the same platform. We still retain am57xx-beagle-x15.dts at this point, since we just require the common minimum dts. As a result of this change, users should expect changes in build procedures('make am57xx_evm_nodt_defconfig' instead of 'make beagle_x15_defconfig'). Hopefully, this would be a one-time change. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-222-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()Kishon Vijay Abraham I2015-08-281-30/+0
| | | | | | | | | | Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-281-0/+97
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-282-0/+18
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-281-0/+9
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-283-0/+9
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-172-0/+45
| | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-121-8/+10
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72: disable workaround for 801819Nishanth Menon2015-08-121-0/+11
| | | | | | | | | | | | | | | | | DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-121-0/+6
| | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* omap5: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-272-0/+47
| | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* ARM: DRA7: Change configuration to prevent DDR reset control from EMIFNishanth Menon2015-06-191-4/+4
| | | | | | | | | | | | | | | | | | | | DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an external entity might be in control of things. The default configuration of Linux on TI evms involve not powering off the voltage rails (due to various reasons including reliability concerns) and must not allow DDR reset to be controlled by EMIF. On platforms where external entity might control the reset signal, this configuration will be a "dont care". Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers") Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-151-1/+2
| | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-152-0/+11
| | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-121-1/+100
| | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-123-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-121-0/+9
| | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-121-2/+2
| | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-121-8/+8
| | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-121-4/+8
| | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-121-6/+11
| | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-121-6/+16
| | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-121-3/+73
| | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arch: Make board selection choices optionalJoe Hershberger2015-05-121-0/+1
| | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Set serial number environment variableDileep Katta2015-04-231-0/+4
| | | | | | | | | | | | | | | | | This patch populates serial number environment variable from die_id_0 and die_id_1 register values for DRA7xx boards. The function is added in omap common code so that this can be re-used. Serial# environment variable will be useful to show correct information in "fastboot devices" commands. Ref: http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.cKishon Vijay Abraham I2015-04-161-2/+2
| | | | | | | | | | | | | | | | Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY) changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between the two dwc3 controllers present in dra7xx/am43xx and enabled these clocks in enable_basic_clocks() in hw_data.c. However these clocks continued to be enabled in board files/driver files for dwc3 host mode functionality causing compilation break with few configs. Fixed it here by making all the clocks enabled in enable_basic_clocks() and removing it from board files/driver files here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* ARM: DRA7: Enable clocks for USB OTGSS and USB PHYKishon Vijay Abraham I2015-04-142-5/+19
| | | | | | | Enabled clocks for dwc3 controller and USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configurationNishanth Menon2015-03-131-0/+16
| | | | | | | | | | | Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance. These apply to both OMAP5 and DRA7. Reported-by: Vivek Chengalvala <vchengalvala@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao2015-03-131-0/+7
| | | | | | | | | | | | | | | | | | | This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7-evm: DDR3: Update leveling valuesLokesh Vutla2015-02-161-30/+30
| | | | | | | Update the software leveling parameters. This fixes the random crash seen on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register valueLokesh Vutla2015-02-161-3/+6
| | | | | | | | | | | The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clockAngela Stegmaier2015-02-161-8/+8
| | | | | | | | | | DDR3 timing and latency paramenters were not configured correctly for 666MHz. Fixing the timing and latency values according to Data sheet. This fixes the random crashes seen on DRA72-evm. Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-291-19/+24
| | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* beagle_x15: add board support for Beagle x15Felipe Balbi2014-12-041-0/+4
| | | | | | | | | | | | | | | | | BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet. For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: sdram: mark emif_get_ext_phy_ctrl_const_regs __weakFelipe Balbi2014-12-041-1/+1
| | | | | | | | this will allow for boards to overwrite those in case memory setup is different. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: make hw_init_data weakFelipe Balbi2014-12-041-1/+1
| | | | | | | | this way we can let boards overwrite based on what they need. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: prcm: add missing registersFelipe Balbi2014-12-041-0/+3
| | | | | | | | | some boards might want to use USB1 for host, without fiddling those registers it'll be impossible. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-041-5/+5
| | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
OpenPOWER on IntegriCloud