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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-02-16 10:15:56 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-02-16 12:41:40 -0500 |
| commit | 802bb57a584db2202a47d41ac730fe76ddeb4f33 (patch) | |
| tree | 499ccc1cbbb52182227112a9fb7eb37fc7bfafe9 /arch/arm/cpu/armv7/omap5 | |
| parent | aa8ac43645243b69faf0e81fab5f0d6fcf4285cf (diff) | |
| download | talos-obmc-uboot-802bb57a584db2202a47d41ac730fe76ddeb4f33.tar.gz talos-obmc-uboot-802bb57a584db2202a47d41ac730fe76ddeb4f33.zip | |
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index e5456ff7cb..61e9aefe09 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61851ab2, .sdram_config = 0x61851ab2, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, @@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, @@ -189,7 +191,8 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61862B32, .sdram_config = 0x61862B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000144A, + .ref_ctrl = 0x0000493E, + .ref_ctrl_final = 0x0000144A, .sdram_tim1 = 0xD113781C, .sdram_tim2 = 0x308F7FE3, .sdram_tim3 = 0x009F86A8, |
