summaryrefslogtreecommitdiffstats
path: root/arch/arm/cpu/armv7/omap5
diff options
context:
space:
mode:
authorLokesh Vutla <lokeshvutla@ti.com>2015-06-03 14:43:24 +0530
committerTom Rini <trini@konsulko.com>2015-06-12 12:43:06 -0400
commitf308b4fce5d0c8a9ebae1e369d4b188f9432f79c (patch)
treee64b1b06f5c799772e4b9c7a1e9f222c0fab2e6d /arch/arm/cpu/armv7/omap5
parent920638fa5e781de91bb70fb516219c8cd4136407 (diff)
downloadtalos-obmc-uboot-f308b4fce5d0c8a9ebae1e369d4b188f9432f79c.tar.gz
talos-obmc-uboot-f308b4fce5d0c8a9ebae1e369d4b188f9432f79c.zip
ARM: DRA72-evm: Enable HW leveling
Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 942a80a8b4..3022b9e06e 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000493E,
+ .ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x308F7FE3,
- .sdram_tim3 = 0x009F86A8,
+ .sdram_tim2 = 0x305A7FDA,
+ .sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
+ .zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
@@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@@ -533,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
0x0,
0x0,
0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
0x0
};
OpenPOWER on IntegriCloud