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-rw-r--r--board/ti/am335x/MAINTAINERS1
-rw-r--r--board/ti/am335x/board.c157
-rw-r--r--board/ti/am335x/board.h5
-rw-r--r--board/ti/am335x/mux.c31
-rw-r--r--board/ti/am43xx/MAINTAINERS2
-rw-r--r--board/ti/am43xx/board.c78
-rw-r--r--board/ti/am43xx/board.h14
-rw-r--r--board/ti/am43xx/mux.c2
-rw-r--r--board/ti/am57xx/board.c218
-rw-r--r--board/ti/dra7xx/MAINTAINERS5
-rw-r--r--board/ti/dra7xx/evm.c21
-rw-r--r--board/ti/ks2_evm/board.c4
-rw-r--r--board/ti/ks2_evm/board_k2g.c16
13 files changed, 420 insertions, 134 deletions
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 7dc2b83839..c99e06dc10 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -6,7 +6,6 @@ F: include/configs/am335x_evm.h
F: configs/am335x_boneblack_defconfig
F: configs/am335x_boneblack_vboot_defconfig
F: configs/am335x_evm_defconfig
-F: configs/am335x_gp_evm_defconfig
F: configs/am335x_evm_nor_defconfig
F: configs/am335x_evm_norboot_defconfig
F: configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4330be6499..56f4984f47 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -11,11 +11,13 @@
#include <common.h>
#include <errno.h>
#include <spl.h>
+#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
@@ -37,7 +39,13 @@
DECLARE_GLOBAL_DATA_PTR;
/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
#if defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
@@ -52,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void)
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
}
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+ if (board_is_icev2())
+ return &eserial4_device;
+ else
+ return &eserial1_device;
+}
+#endif
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
@@ -97,6 +115,13 @@ static const struct ddr_data ddr3_evm_data = {
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
};
+static const struct ddr_data ddr3_icev2_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
@@ -130,6 +155,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+ .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -162,6 +198,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
PHY_EN_DYN_PWRDN,
};
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+ .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+ PHY_EN_DYN_PWRDN,
+};
+
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
@@ -339,7 +386,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
- else if (board_is_bone_lt())
+ else if (board_is_bone_lt() || board_is_icev2())
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later())
return &dpll_ddr_evm_sk;
@@ -418,6 +465,11 @@ void sdram_init(void)
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
+ if (board_is_icev2()) {
+ gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+ }
+
if (board_is_evm_sk())
config_ddr(303, &ioregs_evmsk, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
@@ -429,12 +481,59 @@ void sdram_init(void)
else if (board_is_evm_15_or_later())
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+ else if (board_is_icev2())
+ config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+ &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+ 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void request_and_set_gpio(int gpio, char *name)
+{
+ int ret;
+
+ ret = gpio_request(gpio, name);
+ if (ret < 0) {
+ printf("%s: Unable to request %s\n", __func__, name);
+ return;
+ }
+
+ ret = gpio_direction_output(gpio, 0);
+ if (ret < 0) {
+ printf("%s: Unable to set %s as output\n", __func__, name);
+ goto err_free_gpio;
+ }
+
+ gpio_set_value(gpio, 1);
+
+ return;
+
+err_free_gpio:
+ gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+ .id = 0x81,
+ .capacitor = 0x90,
+ .mux = 0x6d,
+ .pdiv2 = 0x2,
+ .pdiv3 = 0x2,
+};
+#endif
+
/*
* Basic board specific setup. Pinmux has been handled already.
*/
@@ -448,6 +547,23 @@ int board_init(void)
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
+ int rv;
+
+ if (board_is_icev2()) {
+ REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+ REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+
+ rv = setup_clock_synthesizer(&cdce913_data);
+ if (rv) {
+ printf("Clock synthesizer setup failed %d\n", rv);
+ return rv;
+ }
+ }
+#endif
+
return 0;
}
@@ -515,6 +631,12 @@ static struct cpsw_platform_data cpsw_data = {
};
#endif
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+ defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
@@ -526,11 +648,6 @@ static struct cpsw_platform_data cpsw_data = {
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
- && defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
@@ -581,6 +698,12 @@ int board_eth_init(bd_t *bis)
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
+ } else if (board_is_icev2()) {
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[0].phy_addr = 1;
+ cpsw_slaves[1].phy_addr = 3;
} else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -632,3 +755,23 @@ int board_eth_init(bd_t *bis)
#endif
#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+ return 0;
+ else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+ return 0;
+ else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+ return 0;
+ else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+ return 0;
+ else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+ return 0;
+ else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 062c34512f..9776df7959 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -47,6 +47,11 @@ static inline int board_is_evm_15_or_later(void)
strncmp("1.5", board_ti_get_rev(), 3) <= 0);
}
+static inline int board_is_icev2(void)
+{
+ return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fdf827fe54..8afa5f9b40 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -135,6 +135,11 @@ static struct module_pin_mux gpio0_7_pin_mux[] = {
{-1},
};
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+ {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
+ {-1},
+};
+
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
@@ -172,6 +177,20 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
@@ -237,6 +256,12 @@ static struct module_pin_mux bone_norcape_pin_mux[] = {
};
#endif
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+ {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
+ {-1},
+};
+
#if defined(CONFIG_NOR_BOOT)
void enable_norboot_pin_mux(void)
{
@@ -365,6 +390,12 @@ void enable_board_pin_mux(void)
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ } else if (board_is_icev2()) {
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(gpio0_18_pin_mux);
+ configure_module_pin_mux(uart3_icev2_pin_mux);
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
} else {
puts("Unknown board, cannot configure pinmux.");
hang();
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 96ef85b462..3d40b171d2 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -7,5 +7,3 @@ F: configs/am43xx_evm_defconfig
F: configs/am43xx_evm_qspiboot_defconfig
F: configs/am43xx_evm_ethboot_defconfig
F: configs/am43xx_evm_usbhost_boot_defconfig
-F: configs/am437x_gp_evm_defconfig
-F: configs/am437x_sk_evm_defconfig
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d208d2fa89..bde5ac7c99 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -341,7 +341,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
- else if (board_is_gpevm() || board_is_sk())
+ else if (board_is_evm() || board_is_sk())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
@@ -553,7 +553,7 @@ void sdram_init(void)
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
- } else if (board_is_gpevm()) {
+ } else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
@@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = {
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+ ti_usb_phy_uboot_init(&usb_phy1_device);
+ dwc3_uboot_init(&usb_otg_ss1);
}
-
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
}
-
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
@@ -846,3 +846,19 @@ int board_eth_init(bd_t *bis)
return rv;
}
#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+ return 0;
+ else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+ return 0;
+ else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+ return 0;
+ else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 2cf7a7751d..3f93d13727 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -37,14 +37,24 @@ static inline int board_is_idk(void)
return board_ti_is("AM43_IDK");
}
+static inline int board_is_hsevm(void)
+{
+ return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+ return board_is_gpevm() || board_is_hsevm();
+}
+
static inline int board_is_evm_14_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
}
static inline int board_is_evm_12_or_later(void)
{
- return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
+ return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
}
void enable_uart0_pin_mux(void);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index e03b1bcfaa..f26b21e869 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -126,7 +126,7 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mdio_pin_mux);
- if (board_is_gpevm()) {
+ if (board_is_evm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 86b8f6e895..ccf97b2b13 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36ab,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x409f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36ab,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x409f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
@@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851b32,
- .sdram_config = 0x61851b32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36b3,
- .sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x407f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
+ .sdram_tim1 = 0xcccf36b3,
+ .sdram_tim2 = 0x308f7fda,
+ .sdram_tim3 = 0x407f88a8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -216,41 +216,77 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA752,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA752,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA752,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA752,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA752,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data am572x_idk_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
@@ -315,11 +351,18 @@ invalid_eeprom:
#endif /* CONFIG_SPL_BUILD */
+void vcores_init(void)
+{
+ if (board_is_am572x_idk())
+ *omap_vcores = &am572x_idk_volts;
+ else
+ *omap_vcores = &beagle_x15_volts;
+}
+
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &beagle_x15_volts;
*ctrl = &dra7xx_ctrl;
}
@@ -439,6 +482,19 @@ static struct ti_usb_phy_device usb_phy2_device = {
.index = 1,
};
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
@@ -448,31 +504,23 @@ int board_usb_init(int index, enum usb_init_type init)
printf("port %d can't be used as device\n", index);
disable_usb_clocks(index);
return -EINVAL;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
- OTG_SS_CLKCTRL_MODULEMODE_HW |
- OPTFCLKEN_REFCLK960M);
}
-
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_DWC3
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
+#endif
} else {
printf("port %d can't be used as host\n", index);
disable_usb_clocks(index);
return -EINVAL;
}
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
@@ -483,31 +531,24 @@ int board_usb_init(int index, enum usb_init_type init)
int board_usb_cleanup(int index, enum usb_init_type init)
{
+#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
+ if (init == USB_INIT_DEVICE) {
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ }
break;
default:
printf("Invalid Controller Index\n");
}
+#endif
disable_usb_clocks(index);
return 0;
}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
@@ -686,3 +727,12 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 3f638d0a7e..46b6e82b36 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -3,8 +3,5 @@ M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
F: board/ti/dra7xx/
F: include/configs/dra7xx_evm.h
-F: configs/dra72_evm_defconfig
-F: configs/dra74_evm_defconfig
F: configs/dra7xx_evm_defconfig
-F: configs/dra7xx_evm_qspiboot_defconfig
-F: configs/dra7xx_evm_uart3_defconfig
+F: configs/dra7xx_hs_evm_defconfig
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9bd71d87ba..3fbbc9b23b 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -718,3 +718,24 @@ int board_early_init_f(void)
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_dra72x() && !strcmp(name, "dra72-evm"))
+ return 0;
+ else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+ return 0;
+ else
+ return -1;
+}
+#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 9e8ad932d4..1de7df00b4 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -131,7 +131,7 @@ u32 spl_boot_device(void)
}
#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
@@ -273,4 +273,4 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c412250..8f16845d8e 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+ /* Unlock the reset mux register */
+ clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+ /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+ clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+ RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+ /* lock the reset mux register to prevent any spurious writes. */
+ setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
int board_early_init_f(void)
{
init_plls();
k2g_mux_config();
+ k2g_reset_mux_config();
+
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
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